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Hitachi Single-Chip Microcomputer
H8/3318
H8/3318
HD6473318, HD6433318
Hardware Manual
ADE-602-097A Rev. 2.0 3/6/03 Hitachi, Ltd.
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Preface
The H8/3318 comprises high-performance microcontrollers with a fast H8/300 CPU core and a set of on-chip supporting functions optimized for embedded control. These include ROM, RAM, three types of timers, a programmable timing pattern controller, data transfer unit (with 256-byte DPRAM function), parallel buffer interface, serial communication interface, A/D converter, I/O ports, and other functions needed in control system configurations, so that compact, highperformance systems can be implemented easily. The H8/3318 includes the H8/3318, with 60kbyte ROM and 4-kbyte RAM. A ZTATTM (Zero Turn Around Time) version of the H8/3318 is also available, with userprogrammable PROM, providing a quick and flexible response under all sorts of production conditions, even for applications with frequently-changing specifications. This manual describes the hardware of the H8/3318. Refer to the H8/300 Series Programming Manual for a detailed description of the instruction set.
Contents
Section 1
1.1 1.2 1.3
Overview............................................................................................................ 1 Overview ............................................................................................................................ 1 Block Diagram.................................................................................................................... 5 Pin Assignments and Functions.......................................................................................... 6 1.3.1 Pin Arrangement ................................................................................................... 6 1.3.2 Pin Assignments in Each Operating Mode ........................................................... 8 1.3.3 Pin Functions......................................................................................................... 12 CPU...................................................................................................................... 19
19 19 20 20 21 21 21 22 23 24 25 26 26 28 32 34 36 37 38 40 45 47 48 50 50 51 51 52 52 52
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Section 2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Overview ............................................................................................................................ 2.1.1 Features ................................................................................................................. 2.1.2 Address Space ....................................................................................................... 2.1.3 Register Configuration .......................................................................................... Register Descriptions.......................................................................................................... 2.2.1 General Registers .................................................................................................. 2.2.2 Control Registers................................................................................................... 2.2.3 Initial Register Values ........................................................................................... Data Formats ...................................................................................................................... 2.3.1 Data Formats in General Registers........................................................................ 2.3.2 Memory Data Formats .......................................................................................... Addressing Modes.............................................................................................................. 2.4.1 Addressing Mode .................................................................................................. 2.4.2 Calculation of Effective Address .......................................................................... Instruction Set .................................................................................................................... 2.5.1 Data Transfer Instructions ..................................................................................... 2.5.2 Arithmetic Operations ........................................................................................... 2.5.3 Logic Operations ................................................................................................... 2.5.4 Shift Operations .................................................................................................... 2.5.5 Bit Manipulations.................................................................................................. 2.5.6 Branching Instructions .......................................................................................... 2.5.7 System Control Instructions.................................................................................. 2.5.8 Block Data Transfer Instruction............................................................................ CPU States.......................................................................................................................... 2.6.1 Overview ............................................................................................................... 2.6.2 Program Execution State ....................................................................................... 2.6.3 Exception-Handling State...................................................................................... 2.6.4 Power-Down State ................................................................................................ Access Timing and Bus Cycle............................................................................................ 2.7.1 Access to On-Chip Memory (RAM and ROM)....................................................
2.7.2
Access to On-Chip Register Field and External Devices...................................... 54
Section 3
3.1
MCU Operating Modes and Address Space............................................ 57
57 57 57 58 60 61
3.2 3.3 3.4
Overview ............................................................................................................................ 3.1.1 Mode Selection...................................................................................................... 3.1.2 Mode and System Control Registers ..................................................................... System Control Register (SYSCR) .................................................................................... Mode Control Register (MDCR)........................................................................................ Address Space Map in Each Operating Mode....................................................................
Section 4
4.1 4.2
Exception Handling ........................................................................................ 63
63 63 63 63 66 66 66 68 71 71 72 77 78 79
4.3
4.4
Overview ............................................................................................................................ Reset ................................................................................................................................... 4.2.1 Overview ............................................................................................................... 4.2.2 Reset Sequence...................................................................................................... 4.2.3 Disabling of Interrupts after Reset ........................................................................ Interrupts ............................................................................................................................ 4.3.1 Overview ............................................................................................................... 4.3.2 Interrupt-Related Registers ................................................................................... 4.3.3 External Interrupts................................................................................................. 4.3.4 Internal Interrupts.................................................................................................. 4.3.5 Interrupt Handling ................................................................................................. 4.3.6 Interrupt Response Time ....................................................................................... 4.3.7 Precaution.............................................................................................................. Note on Stack Handling......................................................................................................
Section 5
5.1
Data Transfer Unit .......................................................................................... 81
5.2
Overview ............................................................................................................................ 81 5.1.1 Features ................................................................................................................. 81 5.1.2 Block Diagram ...................................................................................................... 85 5.1.3 Input and Output Pins............................................................................................ 86 5.1.4 Register Configuration .......................................................................................... 87 Register Descriptions.......................................................................................................... 89 5.2.1 I/O Control Register (IOCR)................................................................................. 90 5.2.2 Data Transfer Control Registers A, B, and C (DTCRA, DTCRB, DTCRC)........ 92 5.2.3 Data Transfer Address Register H (DTARH) ....................................................... 95 5.2.4 Data Transfer Address Registers A, B, and C (DTARA, DTARB, DTARC) ...... 96 5.2.5 Reload Address Registers A, B, and C (RLARA, RLARB, RLARC).................. 97 5.2.6 Compare Address Register B (CPARB) ............................................................... 97 5.2.7 Serial/Timer Control Register (STCR) ................................................................. 98 5.2.8 DPRAM Data Registers (DPDRWH, DPDRWL, DPDRRH, DPDRRL) ............ 99 5.2.9 DPRAM Data Register Read Query (DPDRRQ).................................................. 102 5.2.10 Parallel Communication Control/Status Register (PCCSR) ................................. 102
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5.3
5.4
5.2.11 System Control Register (SYSCR) ....................................................................... 107 Operation ............................................................................................................................ 108 5.3.1 DTU Operation...................................................................................................... 108 5.3.2 DTU and PBI Initialization ................................................................................... 115 5.3.3 I/O Transfer Operations ........................................................................................ 116 5.3.4 Buffer Query in DPRAM Mode............................................................................ 120 5.3.5 Operation in DPRAM Bound Buffer Mode .......................................................... 122 5.3.6 Operation in DPRAM Direct Word Mode ............................................................ 129 5.3.7 Operation in Handshake Mode.............................................................................. 133 Application Notes............................................................................................................... 140 5.4.1 DTU and PBI Processing Time ............................................................................. 140
Section 6
6.1
6.2 6.3
Wait-State Controller ..................................................................................... 143 Overview ............................................................................................................................ 143 6.1.1 Features ................................................................................................................. 143 6.1.2 Block Diagram ...................................................................................................... 143 6.1.3 Input/Output Pins .................................................................................................. 144 6.1.4 Register Configuration .......................................................................................... 144 Register Description ........................................................................................................... 144 6.2.1 Wait-State Control Register (WSCR) ................................................................... 144 Wait Modes ........................................................................................................................ 146 Clock Pulse Generator ................................................................................... 149
Overview ............................................................................................................................ 149 7.1.1 Block Diagram ...................................................................................................... 149 7.1.2 Wait-State Control Register (WSCR) ................................................................... 149 Oscillator Circuit ................................................................................................................ 150 7.2.1 Connecting an External Crystal ............................................................................ 150 7.2.2 Input of External Clock Signal.............................................................................. 152 Duty Adjustment Circuit .................................................................................................... 154 Prescaler ............................................................................................................................. 154
Section 7
7.1
7.2
7.3 7.4
Section 8
8.1 8.2
8.3
I/O Ports ............................................................................................................. 155 Overview ............................................................................................................................ 155 Port 1 .................................................................................................................................. 159 8.2.1 Overview ............................................................................................................... 159 8.2.2 Register Configuration and Descriptions .............................................................. 161 8.2.3 Pin Functions in Each Mode ................................................................................. 162 8.2.4 Input Pull-Up Transistors...................................................................................... 164 Port 2 .................................................................................................................................. 165 8.3.1 Overview ............................................................................................................... 165 8.3.2 Register Configuration and Descriptions .............................................................. 167 8.3.3 Pin Functions in Each Mode ................................................................................. 168
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8.3.4 Input Pull-Up Transistors...................................................................................... 170 Port 3 .................................................................................................................................. 171 8.4.1 Overview ............................................................................................................... 171 8.4.2 Register Configuration and Descriptions .............................................................. 172 8.4.3 Pin Functions in Each Mode ................................................................................. 173 8.4.4 Input Pull-Up Transistors...................................................................................... 175 8.5 Port 4 .................................................................................................................................. 176 8.5.1 Overview ............................................................................................................... 176 8.5.2 Register Configuration and Descriptions .............................................................. 177 8.5.3 Pin Functions in Each Mode ................................................................................. 178 8.6 Port 5 .................................................................................................................................. 183 8.6.1 Overview ............................................................................................................... 183 8.6.2 Register Configuration and Descriptions .............................................................. 183 8.6.3 Pin Functions in Each Mode ................................................................................. 185 8.7 Port 6 .................................................................................................................................. 186 8.7.1 Overview ............................................................................................................... 186 8.7.2 Register Configuration and Descriptions .............................................................. 187 8.7.3 Pin Functions in Each Mode.................................................................................. 188 8.8 Port 7 .................................................................................................................................. 196 8.8.1 Overview ............................................................................................................... 196 8.8.2 Register Configuration and Descriptions .............................................................. 197 8.9 Port 8 .................................................................................................................................. 198 8.9.1 Overview ............................................................................................................... 198 8.9.2 Register Configuration and Descriptions .............................................................. 199 8.9.3 Pin Functions in Each Mode ................................................................................. 200 8.10 Port 9 .................................................................................................................................. 206 8.10.1 Overview ............................................................................................................... 206 8.10.2 Register Configuration and Descriptions .............................................................. 207 8.10.3 Pin Functions in Each Mode ................................................................................. 208 8.11 Application Notes............................................................................................................... 211 8.11.1 Processing when Ports are Not Used .................................................................... 211 8.4
Section 9
9.1
9.2
16-Bit Free-Running Timer 0 ...................................................................... 213 Overview ............................................................................................................................ 213 9.1.1 Features ................................................................................................................. 213 9.1.2 Block Diagram ...................................................................................................... 214 9.1.3 Input and Output Pins............................................................................................ 215 9.1.4 Register Configuration .......................................................................................... 216 Register Descriptions.......................................................................................................... 217 9.2.1 Free-Running Counter (FRC)................................................................................ 217 9.2.2 Output Compare Registers A and B (OCRA and OCRB) .................................... 218 9.2.3 Input Capture Registers A to D (ICRA to ICRD) ................................................. 218 9.2.4 Timer Interrupt Enable Register (TIER) ............................................................... 220
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9.3 9.4
9.5 9.6 9.7
9.2.5 Timer Control/Status Register (TCSR) ................................................................. 222 9.2.6 Timer Control Register (TCR) .............................................................................. 225 9.2.7 Timer Output Compare Control Register (TOCR) ............................................... 227 CPU Interface ..................................................................................................................... 229 Operation ............................................................................................................................ 232 9.4.1 FRC Incrementation Timing ................................................................................. 232 9.4.2 Output Compare Timing ....................................................................................... 234 9.4.3 FRC Clear Timing................................................................................................. 235 9.4.4 Input Capture Timing............................................................................................ 235 9.4.5 Timing of Input Capture Flag (ICF) Setting ......................................................... 238 9.4.6 Setting of Output Compare Flags A and B (OCFA and OCFB) ........................... 239 9.4.7 Setting of FRC Overflow Flag (OVF) .................................................................. 240 Interrupts ............................................................................................................................ 240 Sample Application ............................................................................................................ 241 Application Notes............................................................................................................... 242
Section 10 16-Bit Free-Running Timer 1 ...................................................................... 247
10.1 Overview ............................................................................................................................ 247 10.1.1 Features ................................................................................................................. 247 10.1.2 Block Diagram ...................................................................................................... 248 10.1.3 Input and Output Pins............................................................................................ 249 10.1.4 Register Configuration .......................................................................................... 249 10.2 Register Descriptions.......................................................................................................... 250 10.2.1 Free-Running Counter (FRC)................................................................................ 250 10.2.2 Output Compare Registers A and B (OCRA and OCRB) .................................... 250 10.2.3 Input Capture Register (ICR) ................................................................................ 251 10.2.4 Timer Control Register (TCR) .............................................................................. 251 10.2.5 Timer Control/Status Register (TCSR) ................................................................. 253 10.3 CPU Interface ..................................................................................................................... 256 10.4 Operation ............................................................................................................................ 259 10.4.1 FRC Incrementation Timing ................................................................................. 259 10.4.2 Output Compare Timing ....................................................................................... 261 10.4.3 FRC Clear Timing................................................................................................. 261 10.4.4 Input Capture Timing............................................................................................ 262 10.4.5 Timing of Input Capture Flag (ICF) Setting ......................................................... 263 10.4.6 Setting of FRC Overflow Flag (OVF) .................................................................. 263 10.5 Interrupts ............................................................................................................................ 264 10.6 Sample Application ............................................................................................................ 264 10.7 Application Notes............................................................................................................... 265
Section 11 8-Bit Timers ...................................................................................................... 271
11.1 Overview ............................................................................................................................ 271 11.1.1 Features ................................................................................................................. 271
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11.2
11.3
11.4 11.5 11.6
11.1.2 Block Diagram ...................................................................................................... 272 11.1.3 Input and Output Pins............................................................................................ 273 11.1.4 Register Configuration .......................................................................................... 273 Register Descriptions.......................................................................................................... 274 11.2.1 Timer Counter (TCNT) ......................................................................................... 274 11.2.2 Time Constant Registers A and B (TCORA and TCORB) .................................. 274 11.2.3 Timer Control Register (TCR) .............................................................................. 275 11.2.4 Timer Control/Status Register (TCSR) ................................................................. 278 11.2.5 Serial/Timer Control Register (STCR) ................................................................. 280 Operation ............................................................................................................................ 281 11.3.1 TCNT Incrementation Timing .............................................................................. 281 11.3.2 Compare-Match Timing........................................................................................ 283 11.3.3 External Reset of TCNT........................................................................................ 285 11.3.4 Setting of TCSR Overflow Flag (OVF) ................................................................ 285 Interrupts ............................................................................................................................ 286 Sample Application ............................................................................................................ 286 Application Notes............................................................................................................... 287 11.6.1 Contention between TCNT Write and Clear......................................................... 287 11.6.2 Contention between TCNT Write and Increment ................................................. 288 11.6.3 Contention between TCOR Write and Compare-Match ....................................... 289 11.6.4 Contention between Compare-Match A and Compare-Match B.......................... 290 11.6.5 Incrementation Caused by Changing of Internal Clock Source............................ 290
Section 12 Programmable Timing Pattern Controller................................................ 293
12.1 Overview ............................................................................................................................ 293 12.1.1 Features ................................................................................................................. 293 12.1.2 Block Diagram ...................................................................................................... 294 12.1.3 TPC Pins................................................................................................................ 295 12.1.4 Registers................................................................................................................ 296 12.2 Register Descriptions.......................................................................................................... 297 12.2.1 Port 1 Data Direction Register (P1DDR).............................................................. 297 12.2.2 Port 1 Data Register (P1DR) ................................................................................. 297 12.2.3 Port 2 Data Direction Register (P2DDR).............................................................. 297 12.2.4 Port 2 Data Register (P2DR) ................................................................................. 298 12.2.5 Next Data Register A (NDRA) ............................................................................. 298 12.2.6 Next Data Register B (NDRB).............................................................................. 300 12.2.7 Next Data Enable Register 1 (NDER1) ................................................................ 302 12.2.8 Next Data Enable Register 2 (NDER2) ................................................................ 303 12.2.9 TPC Output Control Register (TPCR) .................................................................. 303 12.2.10 TPC Output Mode Register (TPMR) .................................................................... 306 12.3 Operation ............................................................................................................................ 308 12.3.1 Overview ............................................................................................................... 308 12.3.2 Output Timing ....................................................................................................... 309
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12.3.3 Normal TPC Output .............................................................................................. 310 12.3.4 Non-Overlapping TPC Output .............................................................................. 312 12.4 Application Notes............................................................................................................... 314 12.4.1 Operation of TPC Output Pins .............................................................................. 314 12.4.2 Note on Non-Overlapping Output......................................................................... 314
Section 13 Watchdog Timer .............................................................................................. 317
13.1 Overview ............................................................................................................................ 317 13.1.1 Features ................................................................................................................. 317 13.1.2 Block Diagram ...................................................................................................... 318 13.1.3 Register Configuration .......................................................................................... 318 13.2 Register Descriptions.......................................................................................................... 319 13.2.1 Timer Counter (TCNT) ......................................................................................... 319 13.2.2 Timer Control/Status Register (TCSR) ................................................................. 319 13.2.3 Register Access ..................................................................................................... 321 13.3 Operation ............................................................................................................................ 322 13.3.1 Watchdog Timer Mode ......................................................................................... 322 13.3.2 Interval Timer Mode ............................................................................................. 323 13.3.3 Setting the Overflow Flag ..................................................................................... 323 13.4 Application Notes............................................................................................................... 324 13.4.1 Contention between TCNT Write and Increment ................................................. 324 13.4.2 Changing the Clock Select Bits (CKS2 to CKS0) ................................................ 324 13.4.3 Recovery from Software Standby Mode ............................................................... 324
Section 14 Serial Communication Interface ................................................................. 325
14.1 Overview ............................................................................................................................ 325 14.1.1 Features ................................................................................................................. 325 14.1.2 Block Diagram ...................................................................................................... 326 14.1.3 Input and Output Pins............................................................................................ 327 14.1.4 Register Configuration .......................................................................................... 328 14.2 Register Descriptions.......................................................................................................... 329 14.2.1 Receive Shift Register (RSR)................................................................................ 329 14.2.2 Receive Data Register (RDR) ............................................................................... 329 14.2.3 Transmit Shift Register (TSR) .............................................................................. 329 14.2.4 Transmit Data Register (TDR).............................................................................. 330 14.2.5 Serial Mode Register (SMR)................................................................................. 330 14.2.6 Serial Control Register (SCR)............................................................................... 332 14.2.7 Serial Status Register (SSR).................................................................................. 335 14.2.8 Bit Rate Register (BRR)........................................................................................ 338 14.2.9 Serial/Timer Control Register (STCR) ................................................................. 348 14.2.10 Serial Communication Mode Register (SCMR) ................................................... 348 14.3 Operation ............................................................................................................................ 350 14.3.1 Overview ............................................................................................................... 350
vii
14.3.2 Asynchronous Mode ............................................................................................. 352 14.3.3 Synchronous Mode................................................................................................ 365 14.4 Interrupts ............................................................................................................................ 371 14.5 Application Notes............................................................................................................... 372
Section 15 A/D Converter .................................................................................................. 375
15.1 Overview ............................................................................................................................ 375 15.1.1 Features ................................................................................................................. 375 15.1.2 Block Diagram ...................................................................................................... 376 15.1.3 Input Pins .............................................................................................................. 377 15.1.4 Register Configuration .......................................................................................... 378 15.2 Register Descriptions.......................................................................................................... 379 15.2.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 379 15.2.2 A/D Control/Status Register (ADCSR) ................................................................ 380 15.2.3 A/D Control Register (ADCR).............................................................................. 382 15.3 CPU Interface ..................................................................................................................... 383 15.4 Operation ............................................................................................................................ 384 15.4.1 Single Mode (SCAN = 0)...................................................................................... 384 15.4.2 Scan Mode (SCAN = 1) ........................................................................................ 386 15.4.3 Input Sampling and A/D Conversion Time .......................................................... 388 15.4.4 External Trigger Input Timing .............................................................................. 389 15.5 Interrupts ............................................................................................................................ 390 15.6 Usage Notes........................................................................................................................ 390
Section 16 RAM.................................................................................................................... 395
16.1 Overview ............................................................................................................................ 395 16.1.1 Block Diagram ...................................................................................................... 395 16.1.2 RAM Enable Bit (RAME) in System Control Register (SYSCR)........................ 396 16.2 Operation ............................................................................................................................ 396 16.2.1 Expanded Modes (Modes 1 and 2)........................................................................ 396 16.2.2 Single-Chip Mode (Mode 3) ................................................................................. 396 16.3 Application Notes............................................................................................................... 397 16.3.1 Note on Initial Values ........................................................................................... 397
Section 17 ROM.................................................................................................................... 399
17.1 Overview ............................................................................................................................ 399 17.1.1 Block Diagram ...................................................................................................... 400 17.2 PROM Mode (H8/3318)..................................................................................................... 401 17.2.1 PROM Mode Setup ............................................................................................... 401 17.2.2 Socket Adapter Pin Assignments and Memory Map ............................................ 401 17.3 Programming...................................................................................................................... 403 17.3.1 Programming and Verification.............................................................................. 404 17.3.2 Notes on Programming.......................................................................................... 408
viii
17.3.3 Reliability of Programmed Data ........................................................................... 408 17.3.4 Erasing Data .......................................................................................................... 409 17.4 Handling of Windowed Packages ...................................................................................... 410 17.4.1 Glass Erasing Window.......................................................................................... 410 17.4.2 Handling after Programming ................................................................................ 410 17.4.3 84-Pin LCC Package ............................................................................................. 410
Section 18 Power-Down State .......................................................................................... 411
18.1 Overview ............................................................................................................................ 411 18.1.1 System Control Register (SYSCR) ....................................................................... 412 18.2 Sleep Mode......................................................................................................................... 413 18.2.1 Transition to Sleep Mode ...................................................................................... 413 18.2.2 Exit from Sleep Mode ........................................................................................... 413 18.3 Software Standby Mode ..................................................................................................... 413 18.3.1 Transition to Software Standby Mode .................................................................. 413 18.3.2 Exit from Software Standby Mode........................................................................ 414 18.3.3 Clock Settling Time for Exit from Software Standby Mode ................................ 414 18.3.4 Sample Application of Software Standby Mode................................................... 415 18.3.5 Application Note ................................................................................................... 415 18.4 Hardware Standby Mode.................................................................................................... 416 18.4.1 Transition to Hardware Standby Mode ................................................................. 416 18.4.2 Recovery from Hardware Standby Mode.............................................................. 416 18.4.3 Timing Relationships ............................................................................................ 417
Section 19 Electrical Specifications................................................................................ 419
19.1 Absolute Maximum Ratings............................................................................................... 419 19.2 Electrical Characteristics.................................................................................................... 419 19.2.1 DC Characteristics ................................................................................................ 419 19.2.2 AC Characteristics ................................................................................................ 429 19.2.3 A/D Converter Characteristics .............................................................................. 437 19.3 MCU Operational Timing .................................................................................................. 438 19.3.1 Bus Timing............................................................................................................ 438 19.3.2 Control Signal Timing .......................................................................................... 439 19.3.3 16-Bit Free-Running Timer Timing...................................................................... 441 19.3.4 8-Bit Timer Timing ............................................................................................... 442 19.3.5 Serial Communication Interface Timing............................................................... 443 19.3.6 I/O Port Timing ..................................................................................................... 444 19.3.7 Timing Pattern Controller Timing ........................................................................ 444 19.3.8 DPRAM Timing.................................................................................................... 445 19.3.9 External Clock Output Timing.............................................................................. 449
Appendix A CPU Instruction Set .................................................................................... 451
A.1 Instruction Set List ............................................................................................................. 451
ix
A.2 A.3
Operation Code Map .......................................................................................................... 459 Number of States Required for Execution.......................................................................... 461
Appendix B Register Field................................................................................................ 467
B.1 B.2 Register Addresses and Bit Names .................................................................................... 467 Register Descriptions.......................................................................................................... 472
Appendix C I/O Port Block Diagrams........................................................................... 532
C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 Port 1 Block Diagram......................................................................................................... Port 2 Block Diagram......................................................................................................... Port 3 Block Diagram......................................................................................................... Port 4 Block Diagrams ....................................................................................................... Port 5 Block Diagrams ....................................................................................................... Port 6 Block Diagrams ....................................................................................................... Port 7 Block Diagram......................................................................................................... Port 8 Block Diagrams ....................................................................................................... Port 9 Block Diagrams ....................................................................................................... 532 533 534 535 537 540 546 547 552
Appendix D Pin States........................................................................................................ 559
D.1 Port States in Each Mode ................................................................................................... 559
Appendix E Appendix F
Timing of Transition to and Recovery from Hardware Standby Mode............................................................................................... 561 Product Code Lineup.................................................................................. 562
Appendix G Package Dimensions................................................................................... 563
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Revisions and Additions in this Edition
Page All 8 to 11 13 57 61 81 to 141 144 Item H8/3315 deleted Table 1.2 Pin Assignments in Each Operating Mode Table 1.3 Pin Functions 3.1.1 Mode Selection Figure 3.1 H8/3318 Address Space Map Section 5 Data Transfer Unit 6.2.1 Wait-State Control Register (WSCR) Amended Operating mode control amended Description added Mode 1 amended Totally amended Bit 4 initial value and Read/Write specification amended Bit 4 initial value and Read/Write specification amended Amended Added Amended Amended Amended Notes added and amended Amended Description added Description added Totally amended Revision
149
7.1.2 Wait-State Control Register (WSCR)
203 211 234 261 311 319 326 335 336
Figure 8.20 Pin Functions in Mode 3 (Port 8) 8.11 Application Notes Figure 9.6 Timing of Output Compare A Figure 10.5 Timing of Output Compare A Figure 12.5 Normal TPC Output Example (Five-Phase Pulse Output) 13.2.2 Timer Control/Status Register (TCSR) Figure 14.1 Block Diagram of Serial Communication Interface 14.2.7 Serial Status Register (SSR), Bit 7 14.2.7 Serial Status Register (SSR), Bit 6
338 to 347 Table 14.3 Examples of BRR Settings in Asynchronous Mode (When o P = o) Table 14.6 Examples of BRR Settings in Synchronous Mode (When o P = o/2) 356 361 364 Figure 14.5 Sample Flowchart for Transmitting Serial Data Figure 14.8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit) Figure 14.11 Example of SCI Receive Operation (Eight-Bit Data with Multiprocessor Bit and One Stop Bit)
Description added Amended Amended
Page 369 370
Item Figure 14.16 Example of SCI Receive Operation Figure 14.17 Sample Flowchart for Serial Transmitting and Receiving
Revision Amended Note added Totally amended Added Amended, note added Amended Amended Amended Description added Amended Amended Amended Amended Added Amended
390 to 394 15.6 Usage Notes 397 409 431 439 448 477 495 526 528 558 562 16.3 Application Notes Figure 17.6 Recommended Screening Procedure Table 19.8 Control Signal Timing Figure 19.5 Basic Bus Cycle (with 1 Wait State) in Expanded Modes (Modes 1, 2) Figure 19.23 Receive Timing in Handshake Mode B.2 Register Descriptions SSR--Serial Status Register B.2 Register Descriptions WSCR--Wait-State Control Register B.2 Register Descriptions DTCRB--Data Transfer Control Register B B.2 Register Descriptions DTCRC--Data Transfer Control Register C Figure C.9 (g) Port 9 Block Diagram (Pin P97) Appendix F Product Code Lineup
563 to 566 Appendix G Package Dimensions
Section 1 Overview
1.1 Overview
The H8/3318 consists of single-chip microcomputer units (MCUs) featuring an H8/300 CPU core and a complement of on-chip supporting modules implementing a variety of system functions. The H8/300 CPU is a high-speed processor with an architecture featuring powerful bitmanipulation instructions, ideally suited for realtime control applications. The on-chip supporting modules implement peripheral functions needed in system configurations. These include ROM, RAM, three types of timers (16-bit free-running timers, 8-bit timers, and a watchdog timer), a programmable timing pattern controller (TPC), a data transfer unit (DTU) with a parallel buffer interface (PBI) supporting a 256-byte DPRAM function, a serial communication interface (SCI), an A/D converter, and I/O ports. The H8/3318 can operate in single-chip mode or in two expanded modes, depending on the requirements of the application. The H8/3318 is available in a masked ROM version, or a ZTAT* version with electrically programmable ROM that can be programmed at the user site. Note: * ZTAT is a trademark of Hitachi, Ltd. Table 1.1 lists the features of the H8/3318
1
Table 1.1
Item CPU
Features
Description Two-way general register configuration * * * * * Eight 16-bit registers, or Sixteen 8-bit registers
High-speed operation Maximum clock rate: 16 MHz/5 V, 12 MHz/4 V, and 10 MHz/3 V (o clock) Add/subtract: 125 ns (16 MHz operation), 167 ns (12 MHz operation), and 200 ns (10 MHz operation) Multiply/divide: 875 ns (16 MHz operation), 1167 ns (12 MHz operation), and 1400 ns (10 MHz operation)
Streamlined, concise instruction set * * * * * * * Memory * * Data transfer unit (DTU) (4 channels) 16-bit freerunning timer (2 channels) * * * * * * * Instruction length: 2 or 4 bytes Register-register arithmetic and logic operations MOV instruction for data transfer between registers and memory
Instruction set features Multiply instruction (8 bits x 8 bits) Divide instruction (16 bits / 8 bits) Bit-accumulator instructions Register-indirect specification of bit positions 60-kbyte ROM 4-kbyte RAM 1 channel for PBI transfer (single address) 1 channel for I/O transfer (dual address) 2 channels for either PBI or I/O transfer One 16-bit free-running counter per channel (can also count external events) Two output-compare lines per channel Channel 0: four input capture lines (can be buffered) Channel 1: one input capture line
2
Table 1.1
Item 8-bit timer (2 channels)
Features (cont)
Description Each channel has * * One 8-bit up-counter (can also count external events) Two time constant registers Maximum 16-bit pulse output, using FRT as time base Up to four 4-bit pulse output groups (or one 16-bit group, or two 8-bit groups) Non-overlap mode available Output data can be transferred by DTU Overflow or NMI interrupt can reset the chip Also usable as interval timer Asynchronous or synchronous mode (selectable) Full duplex: can transmit and receive simultaneously On-chip baud rate generator 10-bit resolution Eight channels: single or scan mode (selectable) Start of A/D conversion can be externally triggered Sample-and-hold function 58 input/output lines (16 of which can drive LEDs) Eight input-only lines Nine external interrupt lines: NMI, IRQ0 to IRQ7 33 on-chip interrupt sources Expanded mode with on-chip ROM disabled (mode 1) Expanded mode with on-chip ROM enabled (mode 2) Single-chip mode (mode 3) Sleep mode Software standby mode Hardware standby mode On-chip oscillator
Programmable timing pattern controller (TPC)
* * * *
Watchdog timer (WDT) (1 channel) Serial communication interface (SCI) (2 channels) A/D converter
* * * * * * * * *
I/O ports
* *
Interrupts
* *
Operating modes
* * *
Power-down modes
* * *
Other features
*
3
Table 1.1
Item Series lineup
Features (cont)
Description
Model 5 V Version (16 MHz) 4 V Version (12 MHz) HD6473318CG16 HD6473318CP16 HD6473318F16 HD6473318TF16 H8/3318 HD6433318CP16 HD6433318CP12 HD6433318F16 HD6433318F12 HD6433318TF16 HD6433318TF12
Product Name H8/3318 ZTAT
3 V Version (10 MHz) HD6473318CG16 HD6473318CP16 HD6473318F16 HD6473318TF16
Package 84-pin windowed LCC (CG-84) 84-pin PLCC (CP-84) 80-pin QFP (FP-80A) 80-pin TQFP (TFP-80C)
ROM PROM
HD6433318VCP10 84-pin PLCC (CP-84) HD6433318VF10 HD6433318VTF10 80-pin QFP (FP-80A) 80-pin TQFP (TFP-80C)
Mask ROM
4
1.2
Block Diagram
Figure 1.1 shows a block diagram of the H8/3318.
XTAL EXTAL RES STBY NMI MD0 MD1 VCC VCC VSS VSS VSS VSS VSS VSS * VSS Clock pulse generator CPU H8/300
Data bus (high)
P10/A0/TP0 P11/A1/TP1 P12/A2/TP2 P13/A3/TP3 P14/A4/TP4 P15/A5/TP5 P16/A6/TP6 P17/A7/TP7 P20/A8/TP8 P21/A9/TP9 P22/A10/TP10 P23/A11/TP11 P24/A12/TP12 P25/A13/TP13 P26/A14/TP14 P27/A15/TP15 P60/FTCI/ETMCI0 P61/FTOA0 P62/FTIA/FTI P63/FTIB/ETMRI0 P64/FTIC/ETMO0 P65/FTID/ETMCI1 P66/FTOB0/IRQ6/ETMRI1 P67/IRQ7/ETMO1
Data bus (low) Port 1
Address bus
ROM
RAM
P90/ADTRG/IRQ2 P91/IRQ1/XCS P92/IRQ0 P93/RD/CS P94/WR/OE P95/AS/RDY P94/o P97/WAIT/WE P30/D0/DDB0 P31/D1/DDB1 P32/D2/DDB2 P33/D3/DDB3 P34/D4/DDB4 P35/D5/DDB5 P36/D6/DDB6 P37/D7/DDB7 P80/RS0 P81/RS1 P82/RS2 P83/WRQ/XRDY P84/TxD1/IRQ3/XWE P85/RxD1/IRQ4 P86/SCK1/IRQ5/XOE
Watchdog timer Port 2 Timing pattern controller 16-bit free-running timer (2 channels)
Data transfer unit, DPRAM function Serial communication interface (2 channels) 10-bit A/D converter (8 channels) Port 3 Port 5 P50/TxD0 P51/RxD0 P52/SCK0 Port 8
Port 6
8-bit timer (2 channels)
Port 4 P40/TMCI0/XDDB0 P41/TMO0/XDDB1 P42/TMRI0/XDDB2 P43/TMCI1/XDDB3 P44/TMO1/XDDB4 P45/TMRI1/XDDB5 P46/FTOA1/XDDB6 P47/FTOB1/XDDB7
Port 7 P77/AN7 P76/AN6 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 AVCC AVSS
Note: * CP-84 and CG-84 only.
Figure 1.1 Block Diagram
Port 9
5
1.3
1.3.1
Pin Assignments and Functions
Pin Arrangement
Figure 1.2 shows the pin arrangement of the CP-84 and CG-84 packages. Figure 1.3 shows the pin arrangement of the FP-80A and TFP-80C packages.
P86/SCK1/IRQ5/XOE P85/RxD1/IRQ4 P84/TxD1/IRQ3/XWE P83/WRQ/XRDY P82/RS2 P81/RS1 P80/RS0 VSS P37/D7/DDB7 VSS P36/D6/DDB6 P35/D5/DDB5 P34/D4/DDB4 P33/D3/DDB3 P32/D2/DDB2 P31/D1/DDB1 P30/D0/DDB0 P10/A0/TP0 P11/A1/TP1 P12/A2/TP2 P13/A3/TP3
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
RES XTAL EXTAL MD1 MD0 NMI STBY VCC P52/SCK0 P51/RxD0 P50/TxD0 VSS VSS P97/WAIT/WE P96/o P95/AS/RDY P94/WR/OE P93/RD/CS P92/IRQ0 P91/IRQ1/XCS P90/ADTRG/IRQ2
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54
P14/A4/TP4 P15/A5/TP5 P16/A6/TP6 P17/A7/TP7 VSS P20/A8/TP8 P21/A9/TP9 P22/A10/TP10 P23/A11/TP11 P24/A12/TP12 VSS P25/A13/TP13 P26/A14/TP14 P27/A15/TP15 VCC P47/FTOB1/XDDB7 P46/FTOA1/XDDB6 P45/TMRI1/XDDB5 P44/TMO1/XDDB4 P43/TMCI1/XDDB3 P42/TMRI0/XDDB2
Figure 1.2 Pin Arrangement (CP-84 and CG-84, Top View)
6
P60/FTCI/ETMCI0 P61/FTOA0 P62/FTIA/FTI P63/FTIB/ETMRI0 P64/FTIC/ETMO0 P65/FTID/ETMCI1 P66/FTOB0/IRQ6/ETMRI1 P67/IRQ7/ETMO1 VSS AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVSS P40/TMCI0/XDDB0 P41/TMO0/XDDB1
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
RES XTAL EXTAL MD1 MD0 NMI STBY VCC P52/SCK0 P51/RxD0 P50/TxD0 VSS P97/WAIT/WE P96/o P95/AS/RDY P94/WR/OE P93/RD/CS P92/IRQ0 P91/IRQ1/XCS P90/ADTRG/IRQ2
P86/SCK1/IRQ5/XOE P85/RxD1/IRQ4 P84/TxD1/IRQ3/XWE P83/WRQ/XRDY P82/RS2 P81/RS1 P80/RS0 VSS P37/D7/DDB7 P36/D6/DDB6 P35/D5/DDB5 P34/D4/DDB4 P33/D3/DDB3 P32/D2/DDB2 P31/D1/DDB1 P30/D0/DDB0 P10/A0/TP0 P11/A1/TP1 P12/A2/TP2 P13/A3/TP3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P14/A4/TP4 P15/A5/TP5 P16/A6/TP6 P17/A7/TP7 VSS P20/A8/TP8 P21/A9/TP9 P22/A10/TP10 P23/A11/TP11 P24/A12/TP12 P25/A13/TP13 P26/A14/TP14 P27/A15/TP15 VCC P47/FTOB1/XDDB7 P46/FTOA1/XDDB6 P45/TMRI1/XDDB5 P44/TMO1/XDDB4 P43/TMCI1/XDDB3 P42/TMRI0/XDDB2
Figure 1.3 Pin Arrangement (FP-80A and TFP-80C, Top View)
P60/FTCI/ETMCI0 P61/FTOA0 P62/FTIA/FTI P63/FTIB/ETMRI0 P64/FTIC/ETMO0 P65/FTID/ETMCI1 P66/FTOB0/IRQ6/ETMRI1 P67/IRQ7/ETMO1 AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVSS P40/TMCI0/XDDB0 P41/TMO0/XDDB1
7
1.3.2
Pin Assignments in Each Operating Mode
Table 1.2 lists the assignments of the pins of the CP-84, CG-84, FP-80A, and TFP-80C packages in each operating mode. Table 1.2 Pin Assignments in Each Operating Mode
Expanded Modes Pin No. CP-84 CG-84 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PBI FP-80A Enabled TFP-80C (DPME = 1) 71 -- 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 D6 VSS D7 VSS RS 0 RS 1 RS 2 XWE P85/RxD1/ IRQ4 XOE RES XTAL EXTAL MD1 MD0 NMI STBY VCC P52/SCK0 Mode 1 PBI Disabled (DPME = 0) D6 VSS D7 VSS P80 P81 P82 Mode 2 PBI Disabled (DPME = 0) D6 VSS D7 VSS P80 P81 P82 P83 P84/TxD1/ IRQ3 P85/RxD1/ IRQ4 P86/SCK1/ IRQ5 RES XTAL EXTAL MD1 MD0 NMI STBY VCC P52/SCK0 Single-Chip Mode Mode 3 PBI Disabled (DPME = 0) P36 VSS P37 VSS P80 P81 P82 P83 P84/TxD1/ IRQ3 P85/RxD1/ IRQ4 P86/SCK1/ IRQ5 RES XTAL EXTAL MD1 MD0 NMI STBY VCC P52/SCK0 PBI Enabled (DPME = 1) DDB6 VSS DDB7 VSS RS 0 RS 1 RS 2 WRQ P84/TxD1/ IRQ3 P85/RxD1/ IRQ4 P86/SCK1/ IRQ5 RES XTAL EXTAL MD1 MD0 NMI STBY VCC P52/SCK0 PROM Mode EO6 VSS EO7 VSS NC NC NC NC NC NC NC VPP NC NC VSS VSS EA9 VSS VCC NC
WRQ/XRDY P83 P84/TxD1/ IRQ3 P85/RxD1/ IRQ4 P86/SCK1/ IRQ5 RES XTAL EXTAL MD1 MD0 NMI STBY VCC P52/SCK0
Note: Pins marked NC should be left unconnected. For details on PROM mode, refer to 17.2, PROM Mode.
8
Table 1.2
Pin Assignments in Each Operating Mode (cont)
Expanded Modes Single-Chip Mode Mode 2 PBI Disabled (DPME = 0) P51/RxD0 P50/TxD0 VSS VSS WAIT o AS WR RD P92/IRQ0 P91/IRQ1 P90/IRQ2/ ADTRG P60/FTCI P61/FTOA0 P62/FTIA/ FTI P63/FTIB P64/FTIC P65/FTID P66/FTOB0/ IRQ6 P67/IRQ7 Mode 3 PBI Disabled (DPME = 0) P51/RxD0 P50/TxD0 VSS VSS P97 P96/o P95 P94 P93 P92/IRQ0 P91/IRQ1 P90/IRQ2/ ADTRG P60/FTCI P61/FTOA0 P62/FTIA/ FTI P63/FTIB P64/FTIC P65/FTID P66/FTOB0/ IRQ6 P67/IRQ7 PBI Enabled (DPME = 1) P51/RxD0 P50/TxD0 VSS VSS WE P96/o RDY OE CS P92/IRQ0 P91/IRQ1 P90/IRQ2/ ADTRG P60/FTCI P61/FTOA0 P62/FTIA/ FTI P63/FTIB P64/FTIC P65/FTID P66/FTOB0/ IRQ6 P67/IRQ7 PROM Mode NC NC VSS VSS NC NC NC NC NC PGM EA15 EA16 NC NC NC VCC VCC NC NC NC
Pin No. CP-84 CG-84 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PBI FP-80A Enabled TFP-80C (DPME = 1) 10 11 12 -- 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 P51/RxD0 P50/TxD0 VSS VSS WAIT o AS WR RD P92/IRQ0 XCS P90/IRQ2/ ADTRG
Mode 1 PBI Disabled (DPME = 0) P51/RxD0 P50/TxD0 VSS VSS WAIT o AS WR RD P92/IRQ0 P91/IRQ1 P90/IRQ2/ ADTRG
P60/ETMCI0/ P60/FTCI FTCI P61/FTOA0 P62/FTIA/ FTI P61/FTOA0 P62/FTIA/ FTI
P63/ETMRI0/ P63/FTIB FTIB P64/ETMO0/ FTIC P64/FTIC
P65/ETMCI1/ P65/FTID FTID P66/ETMRI1/ P66/FTOB0/ FTOB0/IRQ6 IRQ6 P67/ETMO1/ IRQ7 P67/IRQ7
Note: Pins marked NC should be left unconnected. For details on PROM mode, refer to 17.2, PROM Mode.
9
Table 1.2
Pin Assignments in Each Operating Mode (cont)
Expanded Modes Single-Chip Mode Mode 2 PBI Disabled (DPME = 0) VSS AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVSS P40/TMCI0 P41/TMO0 P42/TMRI0 P43/TMCI1 P44/TMO1 P45/TMRI1 P46/FTOA1 P47/FTOB1 VCC P27/A 15 /TP15 P26/A 14 /TP14 P25/A 13 /TP13 VSS P24/A 12 /TP12 P23/A 11 /TP11 Mode 3 PBI Disabled (DPME = 0) VSS AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVSS P40/TMCI0 P41/TMO0 P42/TMRI0 P43/TMCI1 P44/TMO1 P45/TMRI1 P46/FTOA1 P47/FTOB1 VCC P27/TP15 P26/TP14 P25/TP13 VSS P24/TP12 P23/TP11 PBI Enabled (DPME = 1) VSS AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVSS P40/TMCI0 P41/TMO0 P42/TMRI0 P43/TMCI1 P44/TMO1 P45/TMRI1 P46/FTOA1 P47/FTOB1 VCC P27/TP15 P26/TP14 P25/TP13 VSS P24/TP12 P23/TP11 PROM Mode VSS VCC NC NC NC NC NC NC NC NC VSS NC NC NC NC NC NC NC NC VCC CE EA14 EA13 VSS EA12 EA11
Pin No. CP-84 CG-84 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 PBI FP-80A Enabled TFP-80C (DPME = 1) -- 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 -- 51 52 VSS AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVSS XDDB0 XDDB1 XDDB2 XDDB3 XDDB4 XDDB5 XDDB6 XDDB7 VCC A15 A14 A13 VSS A12 A11
Mode 1 PBI Disabled (DPME = 0) VSS AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVSS P40/TMCI0 P41/TMO0 P42/TMRI0 P43/TMCI1 P44/TMO1 P45/TMRI1 P46/FTOA1 P47/FTOB1 VCC A15 A14 A13 VSS A12 A11
Note: Pins marked NC should be left unconnected. For details on PROM mode, refer to 17.2, PROM Mode.
10
Table 1.2
Pin Assignments in Each Operating Mode (cont)
Expanded Modes Single-Chip Mode Mode 2 PBI Disabled (DPME = 0) P22/A 10 /TP10 P21/A 9/TP9 P20/A 8/TP8 VSS P17/A 7/TP7 P16/A 6/TP6 P15/A 5/TP5 P14/A 4/TP4 P13/A 3/TP3 P12/A 2/TP2 P11/A 1/TP1 P10/A 0/TP0 D0 D1 D2 D3 D4 D5 Mode 3 PBI Disabled (DPME = 0) P22/TP10 P21/TP9 P20/TP8 VSS P17/TP7 P16/TP6 P15/TP5 P14/TP4 P13/TP3 P12/TP2 P11/TP1 P10/TP0 P30 P31 P32 P33 P34 P35 PBI Enabled (DPME = 1) P22/TP10 P21/TP9 P20/TP8 VSS P17/TP7 P16/TP6 P15/TP5 P14/TP4 P13/TP3 P12/TP2 P11/TP1 P10/TP0 DDB0 DDB1 DDB2 DDB3 DDB4 DDB5 PROM Mode EA10 OE EA8 VSS EA7 EA6 EA5 EA4 EA3 EA2 EA1 EA0 EO0 EO1 EO2 EO3 EO4 EO5
Pin No. CP-84 CG-84 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 PBI FP-80A Enabled TFP-80C (DPME = 1) 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 A10 A9 A8 VSS A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D4 D5
Mode 1 PBI Disabled (DPME = 0) A10 A9 A8 VSS A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D4 D5
Note: Pins marked NC should be left unconnected. For details on PROM mode, refer to 17.2, PROM Mode.
11
1.3.3
Pin Functions
Table 1.3 gives a description of the function of each pin. Table 1.3 Pin Functions
Pin No. Type Power Symbol VCC CP-84 CG-84 19, 60 FP-80A TFP-80C 8, 47 I/O I Name and Function Power: Connected to the power supply. Connect both VCC pins to the system power supply. Ground: Connected to ground (0 V). Connect all V SS pins to system ground (0 V). Crystal: Connected to a crystal oscillator. The crystal frequency should be the same as the desired system clock frequency. When an external clock is input from the EXTAL pin, an inverse-phase clock should be input to the XTAL pin. External crystal: Connected to a crystal oscillator or external clock. The frequency of the external clock should be the same as the desired system clock frequency. See section 7.2, Oscillator Circuit, for examples of connections to a crystal and external clock. System clock: Supplies the system clock to peripheral devices. Reset: A low input causes the chip to reset. Standby: A transition to hardware standby mode (a power-down state) occurs when a low input is received at the STBY pin. Address bus: Address output pins.
VSS
2, 4, 23, 24, 41, 64, 70 13
12, 56, 73 2
I
Clock
XTAL
I
EXTAL
14
3
I
o System control RES STBY
26 12 18
14 1 7
O I I
Address bus Data bus
A15 to A 0
61 to 63, 65 to 69, 71 to 78 3, 1, 84 to 79
48 to 55, 57 to 64 72 to 65
O
D7 to D0
I/O
Data bus: 8-bit bidirectional data bus.
12
Table 1.3
Pin Functions (cont)
Pin No.
Type Bus control
Symbol WAIT
CP-84 CG-84 25
FP-80A TFP-80C 13
I/O I
Name and Function Wait: Requests the CPU to insert wait states into the bus cycle when an external address is accessed. Read: Goes low to indicate that the CPU is reading an external address. Write: Goes low to indicate that the CPU is writing to an external address. Address strobe: Goes low to indicate that there is a valid address on the address bus. Non-maskable interrupt: Highestpriority interrupt request. The NMIEG bit in the system control register determines whether the interrupt is recognized at the rising or falling edge of the NMI input. Interrupt request 0 to 7: Maskable interrupt request pins. Mode: Input pins for setting the MCU operating mode according to the table below. These pins must not be changed during MCU operation. MD1 0 0 MD0 0 1 Mode Mode 0 Mode 1 Description Setting prohibited Expanded mode with on-chip ROM disabled Expanded mode with on-chip ROM enabled Single-chip mode
RD WR AS
29 28 27
17 16 15
O O O
Interrupt signals
NMI
17
6
I
IRQ0 to IRQ7 Operating mode control MD1, MD0
30 to 32, 9 to 11, 39, 40 15 16
18 to 20, 78 to 80, 27, 28 4 5
I
I
1
0
Mode 2
1
1
Mode 3
13
Table 1.3
Pin Functions (cont)
Pin No.
Type 16-bit freerunning timer (FRT)
Symbol FTCI
CP-84 CG-84 33
FP-80A TFP-80C 21
I/O I
Name and Function FRT counter clock input: Input pin for an external clock signal for the freerunning counter (FRC) in FRT0 and FRT1. FRT output compare A: Output pin for output compare A in FRT0 and FRT1. FRT output compare B: Output pin for output compare B in FRT0 and FRT1. FRT input capture A: Input pin for input capture A in FRT0, input pin for input capture in FRT1. FRT input capture B: Input pin for input capture B in FRT0. FRT input capture C: Input pin for input capture C in FRT0. FRT input capture D: Input pin for input capture D in FRT0. 8-bit timer output (channels 0 and 1): Compare-match output pins for the 8-bit timers. 8-bit timer counter clock input (channels 0 and 1): External clock input pins for the 8-bit timer counters. 8-bit timer counter reset input (channels 0 and 1): Inputs at these pins reset the 8-bit timer counters. 8-bit timer output (channels 0 and 1): Compare-match output pins for the 8-bit timers. 8-bit timer counter clock input (channels 0 and 1): External clock input pins for the 8-bit timers. 8-bit timer counter reset input (channels 0 and 1): Inputs at these pins reset the 8-bit timer counters.
FTOA0, FTOA1 FTOB0, FTOB1 FTIA, FTI FTIB FTIC FTID 8-bit timer TMO0, TMO1 TMCI0, TMCI1 TMRI0, TMRI1 8-bit timer (pins used in expanded modes when PBI is enabled) ETMO0, ETMO1 ETMCI0, ETMCI1 ETMRI0, ETMRI1
34 58 39 59 35 35 36 37 38 53 56 52 55 54 57 37 40 33 38 36 39
22 45 27 46 23 23 24 25 26 40 43 39 42 41 44 25 28 21 26 24 27
O O I
I I I O
I
I
O
I
I
14
Table 1.3
Pin Functions (cont)
Pin No.
Type
Symbol
CP-84 CG-84 61 to 63, 65 to 69, 71 to 78
FP-80A TFP-80C 48 to 55, 57 to 64
I/O O
Name and Function TPC output 15 to 0: Pulse output pins.
TP 15 to Programmable timing TP 0 pattern controller (TPC) Serial communication interface (SCI) TxD0, TxD1 RxD0, RxD1 SCK 0, SCK 1 A/D converter AN 7 to AN 0 ADTRG AVCC
22 9 21 10 20 11 50 to 43 32 42
11 78 10 79 9 80 37 to 30 20 29
O
Transmit data (channels 0 and 1): Data output pins for the serial communication interface. Receive data (channels 0 and 1): Data input pins for the serial communication interface. Serial clock (channels 0 and 1): Input/output pins for the serial clock. Analog input: Analog signal input pins for the A/D converter. A/D trigger: External trigger input for starting the A/D converter. Analog reference voltage: Reference voltage pin for the A/D converter. If the A/D converter is not used, connect AVCC to the system power supply. Refer to section 19, Electrical Specifications. Analog ground: Ground pin for the A/D converter. Connect to system ground (0 V). DPRAM data bus: 8-bit bidirectional data bus for DPRAM access by an external CPU. Chip select: Chip select input pin for selecting DPRAM. Register select: Address input pins for accessing DPRAM. Output enable: Output enable input pin for reading DPRAM. Write enable: Write enable input pin for writing to DPRAM.
I
I/O I I I
AVSS
51
38
I
Dual-port RAM (DPRAM)
DDB7 to DDB0 CS RS 2 to RS 0 OE WE
3, 1, 84 to 79 29 7 to 5 28 25
72 to 65
I/O
17 76 to 74 16 13
I I I I
15
Table 1.3
Pin Functions (cont)
Pin No.
Type Dual-port RAM (DPRAM)
Symbol RDY
CP-84 CG-84 27
FP-80A TFP-80C 15
I/O O
Name and Function Ready: Ready output pin for sending interrupt requests to an external CPU. NMOS open-drain output. Wait request: Output pin for sending wait requests to an external CPU. DPRAM data bus: 8-bit bidirectional data bus for DPRAM access by an external CPU. Chip select: Chip select input pin for selecting DPRAM. Register select: Address input pin for accessing DPRAM. Output enable: Output enable input pin for reading DPRAM. Write enable: Write enable input pin for writing to DPRAM. Ready/wait request: Output pin for sending interrupt requests to an external CPU. Port 1: An 8-bit input/output port with programmable MOS input pull-ups and LED driving capability. The direction of each bit can be selected in the port 1 data direction register (P1DDR). Port 2: An 8-bit input/output port with programmable MOS input pull-ups and LED driving capability. The direction of each bit can be selected in the port 2 data direction register (P2DDR). Port 3: An 8-bit input/output port with programmable MOS input pull-ups. The direction of each bit can be selected in the port 3 data direction register (P3DDR).
WRQ Dual-port RAM (DPRAM) (pin functions in expanded modes when PBI is enabled) XDDB7 to XDDB0 XCS RS 2 to RS 0 XOE XWE WRQ/ XRDY I/O ports P17 to P1 0
8 59 to 52
77 46 to 39
O I/O
31 7 to 5 11 9 8
19 76 to 74 80 78 77
I I I I O
71 to 78
57 to 64
I/O
P27 to P2 0
61 to 63, 65 to 69
48 to 55
I/O
P37 to P3 0
3, 1, 84 to 79
72 to 65
I/O
16
Table 1.3
Pin Functions (cont)
Pin No.
Type I/O ports
Symbol P47 to P4 0
CP-84 CG-84 59 to 52
FP-80A TFP-80C 46 to 39
I/O I/O
Name and Function Port 4: An 8-bit input/output port. The direction of each bit can be selected in the port 4 data direction register (P4DDR). Port 5: A 3-bit input/output port. The direction of each bit can be selected in the port 5 data direction register (P5DDR). Port 6: An 8-bit input/output port. The direction of each bit can be selected in the port 6 data direction register (P6DDR). Port 7: An 8-bit input port. Port 8: A 7-bit input/output port. The direction of each bit can be selected in the port 8 data direction register (P8DDR). Port 9: An 8-bit input/output port. The direction of each bit (except for P9 6) can be selected in the port 9 data direction register (P9DDR).
P52 to P5 0
20 to 22
9 to 11
I/O
P67 to P6 0
40 to 33
28 to 21
I/O
P77 to P7 0 P86 to P8 0
50 to 43 11 to 5
37 to 30 80 to 74
I I/O
P97 to P9 0
25 to 32
13 to 20
I/O
17
Section 2 CPU
2.1 Overview
The H8/300 CPU is a fast central processing unit with eight 16-bit general registers (also configurable as 16 eight-bit registers) and a concise instruction set designed for high-speed operation. 2.1.1 Features
The main features of the H8/300 CPU are listed below. * Two-way register configuration Sixteen 8-bit general registers, or Eight 16-bit general registers * Instruction set with 57 basic instructions, including: Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct (Rn) Register indirect (@Rn) Register indirect with displacement (@(d:16, Rn)) Register indirect with post-increment or pre-decrement (@Rn+ or @-Rn) Absolute address (@aa:8 or @aa:16) Immediate (#xx:8 or #xx:16) PC-relative (@(d:8, PC)) Memory indirect (@@aa:8) * Maximum 64-kbyte address space * High-speed operation All frequently-used instructions are executed in two to four states The maximum clock rate is 16 MHz/5 V, 12 MHz/4 V, or 10 MHz/3 V (o clock) 8- or 16-bit register-register add or subtract: 125 ns (16 MHz operation), 167 ns (12 MHz operation), 200 ns (10 MHz operation) 8 x 8-bit multiply: 875 ns (16 MHz operation), 1167 ns (12 MHz operation), 1400 ns (10 MHz operation) 16 / 8-bit divide: 875 ns (16 MHz operation), 1167 ns (12 MHz operation), 1400 ns (10 MHz operation) * Power-down mode SLEEP instruction
19
2.1.2
Address Space
The H8/300 CPU supports an address space with a maximum size of 64 kbytes for program code and data combined. The memory map differs depending on the mode (mode 1, 2, or 3). For details, see section 3.4, Address Space Map in Each Operating Mode. 2.1.3 Register Configuration
Figure 2.1 shows the internal register structure of the H8/300 CPU. There are two groups of registers: the general registers and control registers.
General registers (Rn) 7 R0H R1H R2H R3H R4H R5H R6H R7H Control registers 15 PC 76543210 I UHUNZVC 0 PC: Program counter CCR: Condition code register Carry flag Overflow flag Zero flag Negative flag Half-carry flag Interrupt mask bit User bit User bit (SP) 07 R0L R1L R2L R3L R4L R5L R6L R7L SP: Stack pointer 0
CCR
Figure 2.1 CPU Registers
20
2.2
2.2.1
Register Descriptions
General Registers
All the general registers can be used as both data registers and address registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7). When used as data registers, they can be accessed as 16-bit registers, or the high and low bytes can be accessed separately as 8-bit registers (R0H to R7H and R0L to R7L). R7 also functions as the stack pointer, used implicitly by hardware in processing interrupts and subroutine calls. In assembly-language coding, R7 can also be denoted by the letters SP. As indicated in figure 2.2, R7 (SP) points to the top of the stack.
Unused area SP (R7) Stack area
Figure 2.2 Stack Pointer 2.2.2 Control Registers
The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code register (CCR). (1) Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU will execute. Each instruction is accessed in 16 bits (1 word), so the least significant bit of the PC is ignored (always regarded as 0). (2) Condition Code Register (CCR): This 8-bit register contains internal status information, including carry (C), overflow (V), zero (Z), negative (N), and half-carry (H) flags and the interrupt mask bit (I). Bit 7--Interrupt Mask Bit (I): When this bit is set to 1, all interrupts except NMI are masked. This bit is set to 1 automatically by a reset and at the start of interrupt handling.
21
Bit 6--User Bit (U): This bit can be written and read by software (using the LDC, STC, ANDC, ORC, and XORC instructions). Bit 5--Half-Carry Flag (H): This flag is set to 1 when the ADD.B, ADDX.B, SUB.B, SUBX.B, NEG.B, or CMP.B instruction causes a carry or borrow out of bit 3, and is cleared to 0 otherwise. Similarly, it is set to 1 when the ADD.W, SUB.W, or CMP.W instruction causes a carry or borrow out of bit 11, and cleared to 0 otherwise. It is used implicitly in the DAA and DAS instructions. Bit 4--User Bit (U): This bit can be written and read by software (using the LDC, STC, ANDC, ORC, and XORC instructions). Bit 3--Negative Flag (N): This flag indicates the most significant bit (sign bit) of the result of an instruction. Bit 2--Zero Flag (Z): This flag is set to 1 to indicate a zero result and cleared to 0 to indicate a nonzero result. Bit 1--Overflow Flag (V): This flag is set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0--Carry Flag (C): This flag is used by: * Add and subtract instructions, to indicate a carry or borrow at the most significant bit of the result * Shift and rotate instructions, to store the value shifted out of the most significant or least significant bit * Bit manipulation and bit load instructions, as a bit accumulator The LDC, STC, ANDC, ORC, and XORC instructions enable the CPU to load and store the CCR, and to set or clear selected bits by logic operations. The N, Z, V, and C flags are used in conditional branching instructions (Bcc). For the action of each instruction on the flag bits, see the H8/300 Series Programming Manual. 2.2.3 Initial Register Values
When the CPU is reset, the program counter (PC) is loaded from the vector table and the interrupt mask bit (I) in the CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (R7) is not initialized. The stack pointer should be initialized by software, by the first instruction executed after a reset.
22
2.3
Data Formats
The H8/300 CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data. * Bit manipulation instructions operate on 1-bit data specified as bit n (n = 0, 1, 2, ..., 7) in a byte operand. * All arithmetic and logic instructions except ADDS and SUBS can operate on byte data. * The DAA and DAS instructions perform decimal arithmetic adjustments on byte data in packed BCD form. Each nibble of the byte is treated as a decimal digit. * The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits x 8 bits), and DIVXU (16 bits / 8 bits) instructions operate on word data.
23
2.3.1
Data Formats in General Registers
Data of all the sizes above can be stored in general registers as shown in figure 2.3.
Data Type Register No.
7
Data Format
0
1-bit data
RnH
7
6
5
4
3
2
1
0
Don't care
7
0
1-bit data
RnL
Don't care
7
6
5
4
3
2
1
0
7
0 LSB
Byte data
RnH
MSB
Don't care
7
0 LSB
Byte data
RnL
Don't care
MSB
15
0 LSB
Word data
Rn
MSB
7
4 Upper digit
3 Lower digit
0
4-bit BCD data
RnH
Don't care
7
4 Upper digit
3 Lower digit
0
4-bit BCD data
RnL
Don't care
Legend RnH: Upper digit of general register RnL: Lower digit of general register MSB: Most significant bit LSB: Least significant bit
Figure 2.3 Register Data Formats
24
2.3.2
Memory Data Formats
Figure 2.4 indicates the data formats in memory. Word data stored in memory must always begin at an even address. In word access the least significant bit of the address is regarded as 0. If an odd address is specified, no address error occurs but the access is performed at the preceding even address. This rule affects MOV.W instructions and branching instructions, and implies that only even addresses should be stored in the vector table.
Data Type Address Data Format
7
0
1-bit data Byte data
Address n Address n Even address Odd address Even address Odd address Even address Odd address
7
MSB
6
5
4
3
2
1
0
LSB
Word data
MSB
Upper 8 bits Lower 8 bits LSB
Byte data (CCR) on stack
MSB MSB
CCR CCR*
LSB LSB
Word data on stack
MSB LSB
Note: * Ignored on return Legend CCR: Condition code register
Figure 2.4 Memory Data Formats When the stack is addressed by register R7, it must always be accessed a word at a time. When the CCR is pushed on the stack, two identical copies of the CCR are pushed to make a complete word. When they are restored, the lower byte is ignored.
25
2.4
2.4.1
Addressing Modes
Addressing Mode
The H8/300 CPU supports eight addressing modes. Each instruction uses a subset of these addressing modes. Table 2.1
No. (1) (2) (3) (4)
Addressing Modes
Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Symbol Rn @Rn @(d:16, Rn) @Rn+ @-Rn @aa:8 or @aa:16 #xx:8 or #xx:16 @(d:8, PC) @@aa:8
(5) (6) (7) (8)
Absolute address Immediate Program-counter-relative Memory indirect
(1) Register Direct--Rn: The register field of the instruction specifies an 8- or 16-bit general register containing the operand. In most cases the general register is accessed as an 8-bit register. Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits x 8 bits), and DIVXU (16 bits / 8 bits) instructions have 16-bit operands. (2) Register indirect--@Rn: The register field of the instruction specifies a 16-bit general register containing the address of the operand. (3) Register Indirect with Displacement--@(d:16, Rn): This mode, which is used only in MOV instructions, is similar to register indirect but the instruction has a second word (bytes 3 and 4) which is added to the contents of the specified general register to obtain the operand address. For the MOV.W instruction, the resulting address must be even. (4) Register Indirect with Post-Increment or Pre-Decrement--@Rn+ or @-Rn: * Register Indirect with Post-Increment--@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. It is similar to the register indirect mode, but the 16-bit general register specified in the register field of the instruction is incremented after the operand is accessed. The size of the increment is 1 or 2 depending on the size of the operand: 1 for MOV.B; 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be even.
26
* Register Indirect with Pre-Decrement--@-Rn The @-Rn mode is used with MOV instructions that store register contents to memory. It is similar to the register indirect mode, but the 16-bit general register specified in the register field of the instruction is decremented before the operand is accessed. The size of the decrement is 1 or 2 depending on the size of the operand: 1 for MOV.B; 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be even. (5) Absolute Address--@aa:8 or @aa:16: The instruction specifies the absolute address of the operand in memory. The MOV.B instruction uses an 8-bit absolute address of the form H'FFxx. The upper 8 bits are assumed to be 1, so the possible address range is H'FF00 to H'FFFF (65280 to 65535). The MOV.B, MOV.W, JMP, and JSR instructions can use 16-bit absolute addresses. (6) Immediate--#xx:8 or #xx:16: The instruction contains an 8-bit operand in its second byte, or a 16-bit operand in its third and fourth bytes. Only MOV.W instructions can contain 16-bit immediate values. The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit manipulation instructions contain 3-bit immediate data (#xx:3) in the second or fourth byte of the instruction, specifying a bit number. (7) Program-Counter-Relative--@(d:8, PC): This mode is used to generate branch addresses in the Bcc and BSR instructions. An 8-bit value in byte 2 of the instruction code is added as a sign-extended value to the program counter contents. The result must be an even number. The possible branching range is -126 to +128 bytes (-63 to +64 words) from the current address. (8) Memory Indirect--@@aa:8: This mode can be used by the JMP and JSR instructions. The second byte of the instruction code specifies an 8-bit absolute address from H'0000 to H'00FF (0 to 255). The word located at this address contains the branch address. The upper 8 bits of the absolute address are 0 (H'00), thus the branch address is limited to values from 0 to 255 (H'0000 to H'00FF). Note that some addresses in this area are also located in the vector table. See section 3.4, Address Space Map in Each Operating Mode, for details. If an odd address is specified as a branch destination or as the operand address of a MOV.W instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. See section 2.3.2, Memory Data Formats, for further information.
27
2.4.2
Calculation of Effective Address
Table 2.2 shows how the H8/300 calculates effective addresses in each addressing mode. Arithmetic, logic, and shift instructions use register direct addressing (1). The ADD.B, ADDX.B, SUBX.B, CMP.B, AND.B, OR.B, and XOR.B instructions can also use immediate addressing (6). The MOV instruction uses all the addressing modes except program-counter relative (7) and memory indirect (8). Bit manipulation instructions use register direct (1), register indirect (2), or 8-bit absolute (5) addressing to identify a byte operand, and 3-bit immediate addressing to identify a bit within the byte. The BSET, BCLR, BNOT, and BTST instructions can also use register direct addressing (1) to identify the bit.
28
Table 2.2
No. 1
Effective Address Calculation
Effective Address Calculation Effective Address
3 0 3 0
Addressing Mode and Instruction Format Register direct, Rn
15 87 43 0
regm op regm regn
regn
Operands are contained in registers regm and regn
15 0 15 0
2
Register indirect, @Rn
16-bit register contents
15 76 43 0
op 3
reg
Register indirect with displacement, @(d:16, Rn)
15 76 43 0
15
0 15 0
16-bit register contents
op disp 4
reg
disp
Register indirect with post-increment, @Rn+
15 76 43 0
15
0
15
0
16-bit register contents
op
reg 1 or 2*
Register indirect with pre-decrement, @-Rn
15 76 43 0
15
0 15 0
16-bit register contents
op
reg 1 or 2* Note: * 1 for a byte operand, 2 for a word operand
29
Table 2.2
No. 5
Effective Address Calculation (cont)
Effective Address Calculation Effective Address
15 87 0
Addressing Mode and Instruction Format Absolute address @aa:8
15 87 0
H'FF
op @aa:16
15
abs
0
15
0
op abs 6 Immediate #xx:8
15 87 0
Operand is 1- or 2-byte immediate data IMM
op #xx:16
15
0
op IMM 7
15 0
PC-relative @(d:8, PC)
PC contents
15 0
15
87
0
Sign extension
disp
op
disp
30
Table 2.2
No. 8
Effective Address Calculation (cont)
Effective Address Calculation Effective Address
Addressing Mode and Instruction Format Memory indirect, @@aa:8
15 87 0
op
abs
15 87 0
H'00
15 0
Memory contents (16 bits) Legend reg: General register op: Operation code disp: Displacement IMM: Immediate data abs: Absolute address
31
2.5
Instruction Set
The H8/300 CPU has 57 types of instructions, which are classified by function in table 2.3. Table 2.3
Function Data transfer Arithmetic operations Logic operations Shift Bit manipulation Branch System control Block data transfer
Instruction Classification
Instructions MOV, MOVTPE* , MOVFPE* , PUSH* , POP*
3 3 1 1
Types 3 14 4 8 14 5 8 1 Total 57
ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST Bcc* 2, JMP, BSR, JSR, RTS RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP EEPMOV
Notes: 1. PUSH Rn is equivalent to MOV.W Rn, @-SP. POP Rn is equivalent to MOV.W @SP+, Rn. 2. Bcc is a conditional branch instruction in which cc represents a condition code. 3. Not supported by the H8/3318.
32
The following sections give a concise summary of the instructions in each category, and indicate the bit patterns of their object code. The notation used is defined next. Operation Notation
Rd Rs Rn (EAd) (EAs) SP PC CCR N Z V C #imm #xx:3 #xx:8 #xx:16 disp + - x / General register (destination) General register (source) General register Destination operand Source operand Stack pointer Program counter Condition code register N (negative) flag of CCR Z (zero) flag of CCR V (overflow) flag of CCR C (carry) flag of CCR Immediate data 3-bit immediate data 8-bit immediate data 16-bit immediate data Displacement Addition Subtraction Multiplication Division AND logical OR logical Exclusive OR logical Move Not
33
2.5.1
Data Transfer Instructions
Table 2.4 describes the data transfer instructions. Figure 2.5 shows their object code formats. Table 2.4
Instruction MOV
Data Transfer Instructions
Size* B/W Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:8 or #xx:16, @-Rn, and @Rn+ addressing modes are available for byte or word data. The @aa:8 addressing mode is available for byte data only. The @-R7 and @R7+ modes require word operands. Do not specify byte size for these two modes.
MOVTPE MOVFPE PUSH
B B W
Not supported by the H8/3318. Not supported by the H8/3318. Rn @-SP Pushes a 16-bit general register onto the stack. Equivalent to MOV.W Rn, @-SP.
POP
W
@SP+ Rn Pops a 16-bit general register from the stack. Equivalent to MOV.W @SP+, Rn.
Note: * Size: Operand size B: Byte W: Word
34
15
8
7
0
MOV RmRn
op
15 8 7
rm
rn
0
op
15 8 7
rm
rn
0
@RmRn
op disp
15 8 7
rm
rn
@(d:16, Rm)Rn
0
op
15 8 7
rm
rn
0
@Rm+Rn, or Rn@-Rm
op
15
rn
8 7
abs
0
@aa:8Rn
op abs
15 8 7
rn
@aa:16Rn
0
op
15
rn
8 7
IMM
0
#xx:8Rn
op IMM
15 8 7
rn
#xx:16Rn
0
op abs
15 8 7
rn
MOVFPE, MOVTPE
0
op Legend op: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data
rn
POP, PUSH
Figure 2.5 Data Transfer Instruction Codes
35
2.5.2
Arithmetic Operations
Table 2.5 describes the arithmetic instructions. See figure 2.6 in section 2.5.4, Shift Operations for their object codes. Table 2.5
Instruction ADD SUB
Arithmetic Instructions
Size* B/W Function Rd Rs Rd, Rd + #imm Rd Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register. Word data can be added or subtracted only when both words are in general registers. B Rd Rs C Rd, Rd #imm C Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or addition or subtraction on immediate data and data in a general register. B Rd 1 Rd Increments or decrements a general register. W Rd 1 Rd, Rd 2 Rd Adds or subtracts immediate data to or from data in a general register. The immediate data must be 1 or 2. B Rd decimal adjust Rd Decimal-adjusts (adjusts to packed BCD) an addition or subtraction result in a general register by referring to the CCR. B Rd x Rs Rd Performs 8-bit x 8-bit unsigned multiplication on data in two general registers, providing a 16-bit result.
ADDX SUBX
INC DEC ADDS SUBS DAA DAS MULXU
DIVXU
B
Rd / Rs Rd Performs 16-bit / 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder.
CMP
B/W
Rd - Rs, Rd - #imm Compares data in a general register with data in another general register or with immediate data. Word data can be compared only between two general registers.
NEG
B
0 - Rd Rd Obtains the two's complement (arithmetic complement) of data in a general register.
Note: * Size: Operand size B: Byte W: Word 36
2.5.3
Logic Operations
Table 2.6 describes the four instructions that perform logic operations. See figure 2.6 in section 2.5.4, Shift Operations, for their object codes. Table 2.6
Instruction AND
Logic Operation Instructions
Size* B Function Rd Rs Rd, Rd #imm Rd Performs a logical AND operation on a general register and another general register or immediate data.
OR
B
Rd Rs Rd, Rd #imm Rd Performs a logical OR operation on a general register and another general register or immediate data.
XOR
B
Rd Rs Rd, Rd #imm Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data.
NOT
B
(Rd) (Rd) Obtains the one's complement (logical complement) of general register contents.
Note: * Size: Operand size B: Byte
37
2.5.4
Shift Operations
Table 2.7 describes the eight shift instructions. Figure 2.6 shows the object code formats of the arithmetic, logic, and shift instructions. Table 2.7
Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: * Size: Operand size B: Byte B B B
Shift Instructions
Size* B Function Rd shift Rd Performs an arithmetic shift operation on general register contents. Rd shift Rd Performs a logical shift operation on general register contents. Rd rotate Rd Rotates general register contents. Rd rotate through carry Rd Rotates general register contents through the C (carry) bit.
38
15
8
7
0
op
15 8 7
rm
rn
0
ADD, SUB, CMP, ADDX, SUBX (Rm) ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT
0
op
15 8 7
rn
op
15 8 7
rm
rn
0
MULXU, DIVXU
op
15
rn
8 7
IMM
0
ADD, ADDX, SUBX, CMP (#xx:8)
op
15 8 7
rm
rn
0
AND, OR, XOR (Rm)
op
15
rn
8 7
IMM
0
AND, OR, XOR (#xx:8)
op Legend Operation field op: rm, rn: Register field IMM: Immediate data
rn
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR
Figure 2.6 Arithmetic, Logic, and Shift Instruction Codes
39
2.5.5
Bit Manipulations
Table 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code formats. Table 2.8
Instruction BSET
Bit-Manipulation Instructions
Size* B Function 1 ( of ) Sets a specified bit in a general register or memory to 1. The bit is specified by a bit number, given in 3-bit immediate data or the lower three bits of a general register.
BCLR
B
0 ( of ) Clears a specified bit in a general register or memory to 0. The bit is specified by a bit number, given in 3-bit immediate data or the lower three bits of a general register.
BNOT
B
( of ) ( of ) Inverts a specified bit in a general register or memory. The bit is specified by a bit number, given in 3-bit immediate data or the lower three bits of a general register
BTST
B
( of ) Z Tests a specified bit in a general register or memory and sets or clears the Z flag accordingly. The bit is specified by a bit number, given in 3-bit immediate data or the lower three bits of a general register.
BAND BIAND
B
C ( of ) C ANDs the C flag with a specified bit in a general register or memory. C [ ( of )] C ANDs the C flag with the inverse of a specified bit in a general register or memory. The bit number is specified by 3-bit immediate data. C ( of ) C ORs the C flag with a specified bit in a general register or memory. C [ ( of )] C ORs the C flag with the inverse of a specified bit in a general register or memory. The bit number is specified by 3-bit immediate data. C ( of ) C XORs the C flag with a specified bit in a general register or memory.
BOR BIOR
B
BXOR
B
Note: * Size: Operand size B: Byte
40
Table 2.8
Instruction BIXOR
Bit-Manipulation Instructions (cont)
Size* B Function C [( of )] C XORs the C flag with the inverse of a specified bit in a general register or memory. The bit number is specified by 3-bit immediate data. ( of ) C Copies a specified bit in a general register or memory to the C flag. ( of ) C Copies the inverse of a specified bit in a general register or memory to the C flag. The bit number is specified by 3-bit immediate data. C ( of ) Copies the C flag to a specified bit in a general register or memory. C ( of ) Copies the inverse of the C flag to a specified bit in a general register or memory. The bit number is specified by 3-bit immediate data.
BLD BILD
B
BST BIST
B
Note: * Size: Operand size B: Byte
Notes on Bit Manipulation Instructions: BSET, BCLR, BNOT, BST, and BIST are readmodify-write instructions. They read a byte of data, modify one bit in the byte, then write the byte back. Care is required when these instructions are applied to registers with write-only bits and to the I/O port registers.
Step 1 2 3 Read Modify Write Description Read one data byte at the specified address Modify one bit in the data byte Write the modified data byte back to the specified address
Example 1: BCLR is executed to clear bit 0 in the port 4 data direction register (P4DDR) under the following conditions. P4 7: Input pin, low P4 6: Input pin, high P4 5 - P4 0: Output pins, low The intended purpose of this BCLR instruction is to switch P40 from output to input.
41
Before Execution of BCLR Instruction
P47 Input/output Pin state DDR DR Input Low 0 1 P46 Input High 0 0 P45 Output Low 1 0 P44 Output Low 1 0 P43 Output Low 1 0 P42 Output Low 1 0 P41 Output Low 1 0 P40 Output Low 1 0
Execution of BCLR Instruction BCLR #0, @P4DDR ; clear bit 0 in data direction register
After Execution of BCLR Instruction
P47 Input/output Pin state DDR DR Output Low 1 1 P46 Output High 1 0 P45 Output Low 1 0 P44 Output Low 1 0 P43 Output Low 1 0 P42 Output Low 1 0 P41 Output Low 1 0 P40 Input High 0 0
Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since P4DDR is a write-only register, it is read as H'FF, even though its true value is H'3F. Next the CPU clears bit 0 of the read data, changing the value to H'FE. Finally, the CPU writes this value (H'FE) back to P4DDR to complete the BCLR instruction. As a result, P40DDR is cleared to 0, making P40 an input pin. In addition, P47DDR and P46DDR are set to 1, making P4 7 and P46 output pins.
42
BSET, BCLR, BNOT, BTST
15 8 7 0
op
15 8 7
IMM
rn
0
Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register direct (Rn) Bit No.: register direct (Rm)
0
op
15 8 7
rm
rn
op op
15 8 7
rn IMM
0 0
0 0
0 0
0 Operand: register indirect (@Rn) 0 Bit No.:
0
immediate (#xx:3)
op op
15 8 7
rn rm
0 0
0 0
0 0
0 Operand: register indirect (@Rn) 0 Bit No.:
0
register direct (Rm)
op op
15 8 7
abs IMM 0 0 0
Operand: absolute (@aa:8) 0 Bit No.:
0
immediate (#xx:3)
op op rm
abs 0 0 0
Operand: absolute (@aa:8) 0 Bit No.: register direct (Rm)
BAND, BOR, BXOR, BLD, BST
15 8 7 0
op
15 8 7
IMM
rn
0
Operand: register direct (Rn) Bit No.: immediate (#xx:3)
op op
15 8 7
rn IMM
0 0
0 0
0 0
0 Operand: register indirect (@Rn) 0 Bit No.:
0
immediate (#xx:3)
op op IMM
abs 0 0 0
Operand: absolute (@aa:8) 0 Bit No.: immediate (#xx:3)
Legend op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data
Figure 2.7 Bit Manipulation Instruction Codes
43
BIAND, BIOR, BIXOR, BILD, BIST
15 8 7 0
op
15 8 7
IMM
rn
0
Operand: register direct (Rn) Bit No.: immediate (#xx:3)
op op
15 8 7
rn IMM
0 0
0 0
0 0
0 Operand: register indirect (@Rn) 0 Bit No.:
0
immediate (#xx:3)
op op IMM
abs 0 0 0
Operand: absolute (@aa:8) 0 Bit No.: immediate (#xx:3)
Legend op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data
Figure 2.7 Bit Manipulation Instruction Codes (cont)
44
2.5.6
Branching Instructions
Table 2.9 describes the branching instructions. Figure 2.8 shows their object code formats. Table 2.9
Instruction Bcc
Branching Instructions
Size -- Function Branches if condition cc is true. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE cc field 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Always (true) Never (false) High Low or same Carry clear (High or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1
JMP JSR BSR RTS
-- -- -- --
Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified displacement from the current address. Returns from a subroutine.
45
15
8
7
0
op
15
cc
8 7
disp
0
Bcc
op
15 8 7
rm
0
0
0
0
0
JMP (@Rm)
op abs
15 8 7 0
JMP (@aa:16)
op
15 8 7
abs
0
JMP (@@aa:8)
op
15 8 7
disp
0
BSR
op
15 8 7
rm
0
0
0
0
0
JSR (@Rm)
op abs
15 8 7 0
JSR (@aa:16)
op
15 8 7
abs
0
JSR (@@aa:8)
op Legend op: Operation field cc: Condition field rm: Register field disp: Displacement abs: Absolute address
RTS
Figure 2.8 Branching Instruction Codes
46
2.5.7
System Control Instructions
Table 2.10 describes the system control instructions. Figure 2.9 shows their object code formats. Table 2.10 System Control Instructions
Instruction RTE SLEEP LDC Size* -- -- B Function Returns from an exception-handling routine. Causes a transition to the power-down state. Rs CCR, #imm CCR Moves immediate data or general register contents to the condition code register. STC B CCR Rd Copies the condition code register to a specified general register. ANDC B CCR #imm CCR Logically ANDs the condition code register with immediate data. ORC B CCR #imm CCR Logically ORs the condition code register with immediate data. XORC B CCR #imm CCR Logically exclusive-ORs the condition code register with immediate data. NOP -- PC + 2 PC Only increments the program counter. Note: * Size: Operand size B: Byte
15
8
7
0
op
15 8 7 0
RTE, SLEEP, NOP
op
15 8 7
rn
0
LDC, STC (Rn)
op Legend op: Operation field rn: Register field IMM: Immediate data
IMM
ANDC, ORC, XORC, LDC (#xx:8)
Figure 2.9 System Control Instruction Codes
47
2.5.8
Block Data Transfer Instruction
Table 2.11 describes the EEPMOV instruction. Figure 2.10 shows its object code format. Table 2.11 Block Data Transfer Instruction/EEPROM Write Operation
Instruction EEPMOV Size -- Function if R4L 0 then repeat until else next; Moves a data block according to parameters set in general registers R4L, R5, and R6. R4L: size of block (bytes) R5: starting source address R6: starting destination address Execution of the next instruction starts as soon as the block transfer is completed. @R5+ @R6+ R4L - 1 R4L R4L = 0
15
8
7
0
op op Legend op: Operation field
Figure 2.10 Block Data Transfer Instruction/EEPROM Write Operation Code
48
Notes on EEPMOV Instruction 1. The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified by R5 to the address specified by R6.
R5 R6
R5 + R4L
R6 + R4L
2. When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of the instruction.
R5 R6 H'FFFF Not allowed R6 + R4L
R5 + R4L
49
2.6
2.6.1
CPU States
Overview
The CPU has three states: the program execution state, exception-handling state, and power-down state. The power-down state is further divided into three modes: sleep mode, software standby mode, and hardware standby mode. Figure 2.11 summarizes these states, and figure 2.12 shows a map of the state transitions.
State
Program execution state The CPU executes successive program instructions. Exception-handling state A transient state triggered by a reset or interrupt. The CPU executes a hardware sequence that includes loading the program counter from the vector table. Power-down state A state in which some or all of the chip functions are stopped to conserve power. Sleep mode Software standby mode Hardware standby mode
Figure 2.11 Operating States
50
Exception handing request Exceptionhandling state
Program execution state Exception handing Interrupt request
SLEEP instruction with SSBY bit set SLEEP instruction
Sleep mode
RES = 1
NMI, IRQ0 to IRQ2, or IRQ6
Software standby mode
Reset state
STBY = 1, RES = 0
Hardware standby mode Power-down state
Notes: 1. A transition to the reset state occurs when RES goes low, except when the chip is in the hardware standby mode. 2. A transition from any state to the hardware standby mode occurs when STBY goes low.
Figure 2.12 State Transitions 2.6.2 Program Execution State
In this state the CPU executes program instructions. 2.6.3 Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU is reset or interrupted and changes its normal processing flow. In interrupt exception handling, the CPU references the stack pointer (R7) and saves the program counter and condition code register on the stack. For further details see section 4, Exception Handling.
51
2.6.4
Power-Down State
The power-down state includes three modes: sleep mode, software standby mode, and hardware standby mode. Sleep Mode: Is entered when a SLEEP instruction is executed. The CPU halts, but CPU register contents remain unchanged and the on-chip supporting modules continue to function. Software Standby Mode: Is entered if the SLEEP instruction is executed while the SSBY (software standby) bit in the system control register (SYSCR) is set to 1. The CPU and all on-chip supporting modules halt. The on-chip supporting modules are initialized, but the contents of the on-chip RAM and CPU registers remain unchanged as long as a specified voltage is supplied. I/O port outputs also remain unchanged. Hardware Standby Mode: Is entered when the input at the STBY pin goes low. All chip functions halt, including I/O port output. The on-chip supporting modules are initialized, but onchip RAM contents are held. See section 18, Power-Down State, for further information.
2.7
Access Timing and Bus Cycle
The CPU is driven by the system clock (o). The period from one rising edge of the system clock to the next is referred to as a "state." Memory access is performed in a two- or three-state bus cycle. On-chip memory, on-chip supporting modules, and external devices are accessed in different bus cycles as described below. 2.7.1 Access to On-Chip Memory (RAM and ROM)
On-chip ROM and RAM are accessed in a cycle of two states designated T1 and T2. Either byte or word data can be accessed, via a 16-bit data bus. Figure 2.13 shows the on-chip memory access cycle. Figure 2.14 shows the associated pin states.
52
Bus cycle
T1 state o
T2 state
Internal address bus
Address
Internal read signal
Internal data bus (read)
Read data
Internal write signal
Internal data bus (write)
Write data
Figure 2.13 On-Chip Memory Access Cycle
Bus cycle
T1 state o
T2 state
Address bus
Address
AS: High RD: High WR: High Data bus: high impedance state
Figure 2.14 Pin States during On-Chip Memory Access Cycle
53
2.7.2
Access to On-Chip Register Field and External Devices
The on-chip supporting module registers and external devices are accessed in a cycle consisting of three states: T1, T2, and T3. Only one byte of data can be accessed per cycle, via an 8-bit data bus. Access to word data or instruction codes requires two consecutive cycles (six states). Figure 2.15 shows the access cycle for the on-chip register field. Figure 2.16 shows the associated pin states. Figures 2.17 (a) and (b) show the read and write access timing for external devices.
Bus cycle
T1 state o Internal address bus Internal read signal Internal data bus (read) Internal write signal Internal data bus (write)
T2 state
T3 state
Address
Read data
Write data
Figure 2.15 On-Chip Register Field Access Cycle
54
Bus cycle
T1 state o
T2 state
T3 state
Address bus
Address
AS: High RD: High WR: High Data bus: high impedance state
Figure 2.16 Pin States during On-Chip Register Field Access Cycle
Read cycle
T1 state o
T2 state
T3 state
Address bus
Address
AS
RD
WR: High Data bus
Read data
Figure 2.17 (a) External Device Access Timing (Read)
55
Write cycle
T1 state o
T2 state
T3 state
Address bus
Address
AS
RD: High
WR
Data bus
Write data
Figure 2.17 (b) External Device Access Timing (Write)
56
Section 3 MCU Operating Modes and Address Space
3.1
3.1.1
Overview
Mode Selection
The H8/3318 operates in three modes numbered 1, 2, and 3. The mode is selected by the inputs at the mode pins (MD1 and MD 0) when the chip comes out of a reset. See table 3.1. Table 3.1
Mode Mode 0 Mode 1 Mode 2 Mode 3
Operating Modes
MD1 Low Low High High MD0 Low High Low High Address Space -- Expanded Expanded Single-chip On-Chip ROM -- Disabled Enabled Enabled On-Chip RAM -- Enabled* Enabled* Enabled
Note: * If the RAME bit in the system control register (SYSCR) is cleared to 0, off-chip memory can be accessed instead.
Modes 1 and 2 are expanded modes that permit access to off-chip memory and peripheral devices. The maximum address space supported by these externally expanded modes is 64 kbytes. In mode 3 (single-chip mode), only on-chip ROM and RAM and the on-chip register field are used. All ports are available for general-purpose input and output. Mode 0 is inoperative in the H8/3318. Avoid setting the mode pins to mode 0. In addition, the mode pins must not be changed during MCU operation. 3.1.2 Mode and System Control Registers
Table 3.2 lists the registers related to the chip's operating mode: the system control register (SYSCR) and mode control register (MDCR). The mode control register indicates the inputs to the mode pins MD1 and MD 0. Table 3.2
Name System control register Mode control register
Mode and System Control Registers
Abbreviation SYSCR MDCR Read/Write R/W R Address H'FFC4 H'FFC5
57
3.2
Bit
System Control Register (SYSCR)
7 SSBY 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 XRST 1 R 2 NMIEG 0 R/W 1 DPME 0 R/W 0 RAME 1 R/W
Initial value Read/Write
0 R/W
The system control register (SYSCR) is an 8-bit register that controls the operation of the chip. Bit 7--Software Standby (SSBY): Enables transition to the software standby mode. For details, see section 18, Power-Down State. On recovery from software standby mode by an external interrupt, the SSBY bit remains set to 1. It can be cleared by writing 0.
Bit 7 SSBY 0 1 Description The SLEEP instruction causes a transition to sleep mode The SLEEP instruction causes a transition to software standby mode (Initial value)
Bits 6 to 4--Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the clock settling time when the chip recovers from the software standby mode by an external interrupt. During the selected time the CPU and on-chip supporting modules continue to stand by. These bits should be set according to the clock frequency so that the settling time is at least 8 ms. For specific settings, see section 18.3.3, Clock Settling Time for Exit from Software Standby Mode.
Bit 6 STS2 0 Bit 5 STS1 0 Bit 4 STS0 0 1 1 0 1 1 0 1 -- -- Description Settling time = 8,192 states Settling time = 16,384 states Settling time = 32,768 states Settling time = 65,536 states Settling time = 131,072 states Prohibited (Initial value)
58
Bit 3--External Reset (XRST): Indicates the source of a reset. A reset can be triggered by an external reset input, or by a watchdog timer overflow when the watchdog timer is in operation. XRST is set to 1 by an external reset, and cleared to 0 by a watchdog timer overflow.
Bit 3 XRST 0 1 Description Reset generated by watchdog timer overflow Reset generated by external reset input (Initial value)
Bit 2--NMI Edge (NMIEG): Selects the valid edge of the NMI input.
Bit 2 NMIEG 0 1 Description An interrupt is requested on the falling edge of the NMI input An interrupt is requested on the rising edge of the NMI input (Initial value)
Bit 1--Dual-Port RAM Mode Enable (DPME): Selects whether to put the chip into slave mode.
Bit 1 DPME 0 1 Description The chip is not put into slave mode The chip is put into slave mode (Initial value)
Bit 0--RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized by the rising edge of the RES signal, but is not initialized in the software standby mode.
Bit 0 RAME 0 1 Description The on-chip RAM is disabled The on-chip RAM is enabled (Initial value)
59
3.3
Bit
Mode Control Register (MDCR)
7 -- 6 -- 1 -- 5 -- 1 -- 4 -- 0 -- 3 -- 0 -- 2 -- 1 -- 1 MDS1 * R 0 MDS0 * R
Initial value Read/Write
1 --
Note: * Initialized according to MD1 and MD0 inputs.
The mode control register (MDCR) is an 8-bit register that indicates the operating mode of the chip. Bits 7 to 5--Reserved: These bits cannot be modified and are always read as 1. Bits 4 and 3--Reserved: These bits cannot be modified and are always read as 0. Bit 2--Reserved: This bit cannot be modified and is always read as 1. Bits 1 and 0--Mode Select 1 and 0 (MDS1 and MDS0): These bits indicate the values of the mode pins (MD1 and MD0), thereby indicating the current operating mode of the chip. MDS1 corresponds to MD1 and MDS0 to MD0. These bits can be read but not written. When the mode control register is read, the levels at the mode pins (MD1 and MD 0) are latched in these bits.
60
3.4
Address Space Map in Each Operating Mode
Figure 3.1 shows memory map of the H8/3318 in modes 1, 2, and 3.
Mode 1 Expanded mode without on-chip ROM H'0000 Vector table H'0059 H'005A H'0059 H'005A H'0000 Vector table H'0059 H'005A Mode 2 Expanded mode with on-chip ROM H'0000 Vector table Mode 3 Single-chip mode
External address space
On-chip ROM, 58 kbytes
On-chip ROM, 60 kbytes
H'E77F H'E780 H'EF7F H'EF80 H'EF7F H'EF80
External address space
H'EF7F H'EF80
On-chip RAM*, 4 kbyte
On-chip RAM*, 4 kbytes
On-chip RAM, 4 kbytes
H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF
H'FF7F H'FF7F H'FF80 External address space H'FF87 H'FF88 H'FF88 On-chip register field On-chip register field H'FFFF H'FFFF
Note: * External memory can be accessed at these addresses when the RAME bit in the system control register (SYSCR) is cleared to 0.
Figure 3.1 H8/3318 Address Space Map
61
Section 4 Exception Handling
4.1 Overview
The H8/3318 recognizes only two kinds of exceptions: interrupts and the reset. Table 4.1 indicates their priority and the timing of their hardware exception-handling sequence. Table 4.1
Priority High
Hardware Exception-Handling Sequences and Priority
Type of Exception Reset Interrupt Detection Timing Clock synchronous On completion of instruction execution* Timing of Exception-Handling Sequence The hardware exception-handling sequence begins as soon as RES changes from low to high. When an interrupt is requested, the hardware exception-handling sequence begins at the end of the current instruction, or at the end of the current hardware exception-handling sequence.
Low
Note: * Not detected in the case of the ANDC, ORC, XORC, and LDC instructions.
4.2
4.2.1
Reset
Overview
A reset has the highest exception-handling priority. When the RES pin goes low or if the watchdog timer overflows (when the watchdog timer reset option is selected), all current processing stops and the chip enters the reset state. The internal state of the CPU and the registers of the on-chip supporting modules are initialized. When RES returns from low to high or after watchdog timer reset pulses have stopped, the reset exception-handling sequence starts. 4.2.2 Reset Sequence
The reset state begins when RES goes low or if there is a watchdog timer reset. To ensure correct resetting, at power-on the RES pin should be held low for at least 20 ms. In a reset during operation, the RES pin should be held low for at least 10 system clock cycles. Watchdog timer reset pulse widths must be 518 system clock cycles. For the pin states during a reset, see appendix D, Pin States. When a reset occurs, hardware carries out the following reset exception-handling sequence.
63
1. The internal state of the CPU and the registers of the on-chip supporting modules are initialized, and the I bit in the condition code register (CCR) is set to 1. 2. The CPU loads the program counter with the first word in the vector table (stored at addresses H'0000 and H'0001) and starts program execution. The RES pin should be held low when power is switched off, as well as when power is switched on. Figure 4.1 indicates the timing of the reset sequence in modes 2 and 3. Figure 4.2 indicates the timing in mode 1.
Vector Internal Instruction fetch processing prefetch RES/watchdog reset (internal) o Internal address bus Internal read signal Internal write signal Internal data bus (16 bits) (1) Reset vector address (H'0000) (2) Starting address of program (3) First instruction of program (2) (3)
(1)
(2)
Figure 4.1 Reset Sequence (Mode 2 or 3, Program Stored in On-Chip ROM)
64
Vector fetch
Internal processing
Instruction prefetch
RES/watchdog reset (internal)
o (3) (5) (7)
A15 to A0 (1)
RD
WR (high) (2) (4) (6) (8)
Figure 4.2 Reset Sequence (Mode 1)
D7 to D0 (8 bits)
(1), (3) (2), (4) (5), (7) (6), (8)
Reset vector address: (1) = H'0000, (3) = H'0001 Starting address of program (contents of reset vector): (2) = upper byte, (4) = lower byte Starting address of program: (5) = (2) (4), (7) = (2) (4) + 1 First instruction of program: (6) = first byte, (8) = second byte
65
4.2.3
Disabling of Interrupts after Reset
After a reset, if an interrupt were to be accepted before initialization of the stack pointer (SP: R7), the program counter and condition code register might not be saved correctly, leading to a program crash. To prevent this, all interrupts, including NMI, are disabled immediately after a reset. The first program instruction is therefore always executed. This instruction should initialize the stack pointer (example: MOV.W #xx:16, SP). To confirm the CCR contents after reset exception handling, a CCR manipulation instruction can be executed before the instruction that initializes the stack pointer. All interrupts, including NMI, are disabled immediately after execution of a CCR manipulation instruction. The next instruction should be the instruction that initializes the stack pointer.
4.3
4.3.1
Interrupts
Overview
The interrupt sources include nine input pins for external interrupts (NMI, IRQ0 to IRQ7) and 33 internal sources in the on-chip supporting modules. Table 4.2 lists the interrupt sources in priority order and gives their vector addresses. When two or more interrupts are requested, the interrupt with highest priority is served first. The features of these interrupts are: * NMI has the highest priority and is always accepted. All internal and external interrupts except NMI can be masked by the I bit in the CCR. When the I bit is set to 1, interrupts other than NMI are not accepted. * IRQ0 to IRQ7 can be sensed on the falling edge of the input signal, or level-sensed. The type of sensing can be selected for each interrupt individually. NMI is edge-sensed, and either the rising or falling edge can be selected. * All interrupts are individually vectored. The software interrupt-handling routine does not have to determine what type of interrupt has occurred. * The watchdog timer can be used to generate either an NMI interrupt or OVF interrupt, as needed. Refer to section 13, Watchdog Timer, for details.
66
Table 4.2
Interrupts
Vector No. 0 1 to 2 3 4 5 6 7 8 9 10 11 ICIA0 ICIB0 ICIC0 ICID0 (interrupt capture A) (interrupt capture B) (interrupt capture C) (interrupt capture D) 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Vector Address H'0000 to H'0001 H'0002 to H'0005 H'0006 to H'0007 H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 H'001A to H'001B H'001C to H'001D H'001E to H'001F H'0020 to H'0021 H'0022 to H'0023 H'0024 to H'0025 H'0026 to H'0027 H'0028 to H'0029 H'002A to H'002B H'002C to H'002D H'002E to H'002F H'0030 to H'0031 H'0032 to H'0033 H'0034 to H'0035 H'0036 to H'0037 H'0038 to H'0039 H'003A to H'003B H'003C to H'003D H'003E to H'003F H'0040 to H'0041 Low Priority High
Interrupt Source Reset Reserved NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 16-bit free-running timer 0
OCIA0 (output compare A) OCIB0 (output compare B) FOVI0 16-bit free-running timer 1 ICI1 (overflow) (input capture)
OCIA1 (output compare A) OCIB1 (output compare B) FOVI1 (overflow)
8-bit timer 0
CMI0A (compare match A) CMI0B (compare match B) OVI0 (overflow)
8-bit timer 1
CMI1A (compare match A) CMI1B (compare match B) OVI1 (overflow) (receive error) (receive end) (TDR empty) (TSR empty)
Serial communication interface 0
ERI0 RXI0 TXI0 TEI0
67
Table 4.2
Interrupts (cont)
Vector No. ERI1 RXI1 TXI1 TEI1 (receive error) (receive end) (TDR empty) (TSR empty) (conversion end) (write end) (read end) (transfer end A) (transfer end B) (transfer end C) (overrun error) (watchdog overflow) 33 34 35 36 37 38 39 40 41 42 43 44 Vector Address H'0042 to H'0043 H'0044 to H'0045 H'0046 to H'0047 H'0048 to H'0049 H'004A to H'004B H'004C to H'004D H'004E to H'004F H'0050 to H'0051 H'0052 to H'0053 H'0054 to H'0055 H'0056 to H'0057 H'0058 to H'0059 Low Priority High
Interrupt Source Serial communication interface 1
A/D converter Data transfer unit
ADI MWEI MREI DTIA DTIB DTIC CMPI
Watchdog timer
OVF
Notes: 1. Reset vectors are located at H'0000 and H'0001. 2. H'0002 to H'0005 is a reserved area unavailable to the user.
4.3.2
Interrupt-Related Registers
The interrupt-related registers are the system control register (SYSCR), IRQ sense control register (ISCR), and IRQ enable register (IER). Table 4.3
Name System control register IRQ sense control register IRQ enable register
Registers Read by Interrupt Controller
Abbreviation SYSCR ISCR IER Read/Write R/W R/W R/W Address H'FFC4 H'FFC6 H'FFC7
68
System Control Register (SYSCR)
Bit 7 SSBY Initial value Read/Write 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 XRST 1 R 2 NMIEG 0 R/W 1 DPME 0 R/W 0 RAME 1 R/W
The valid edge on the NMI line is controlled by bit 2 (NMIEG) in the system control register. Bit 2--NMI Edge (NMIEG): Determines whether a nonmaskable interrupt is generated on the falling or rising edge of the NMI input signal.
Bit 2 NMIEG 0 1 Description An interrupt is generated on the falling edge of NMI An interrupt is generated on the rising edge of NMI (Initial state)
See section 3.2, System Control Register, for information on the other SYSCR bits. IRQ Sense Control Register (ISCR)
Bit 7 6 5 4 3 2 1 0
IRQ7SC IRQ6SC IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC Initial value Read/Write 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bits 7 to 0--IRQ7 to IRQ0 Sense Control (IRQ7SC to IRQ0SC): These bits determine whether IRQ7 to IRQ0 are level-sensed or sensed on the falling edge.
Bits 7 to 0 IRQ7SC to IRQ0SC 0 1 Description An interrupt is generated when IRQ7 to IRQ0 inputs are low (Initial state)
An interrupt is generated by the falling edge of the IRQ7 to IRQ0 inputs
69
IRQ Enable Register (IER)
Bit 7 IRQ7E Initial value Read/Write 0 R/W 6 IRQ6E 0 R/W 5 IRQ5E 0 R/W 4 IRQ4E 0 R/W 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W
Bits 7 to 0--IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits enable or disable the IRQ7 to IRQ0 interrupts individually.
Bits 7 to 0 IRQ7E to IRQ0E 0 1 Description IRQ7 to IRQ 0 interrupt requests are disabled IRQ7 to IRQ 0 interrupt requests are enabled (Initial state)
When edge sensing is selected (by setting bits IRQ7SC to IRQ0SC to 1), it is possible for an interrupt-handling routine to be executed even though the corresponding enable bit (IRQ7E to IRQ0E) is cleared to 0 and the interrupt is disabled. If an interrupt is requested while the enable bit (IRQ7E to IRQ0E) is set to 1, the request will be held pending until served. If the enable bit is cleared to 0 while the request is still pending, the request will remain pending, although new requests will not be recognized. If the interrupt mask bit (I) in the CCR is cleared to 0, the interrupt-handling routine can be executed even though the enable bit is now 0. If execution of interrupt-handling routines under these conditions is not desired, it can be avoided by using the following procedure to disable and clear interrupt requests. 1. Set the I bit to 1 in the CCR, masking interrupts. Note that the I bit is set to 1 automatically when execution jumps to an interrupt vector. 2. Clear the desired bits from IRQ7E to IRQ0E to 0 to disable new interrupt requests. 3. Clear the corresponding IRQ7SC to IRQ0SC bits to 0, then set them to 1 again. Pending IRQn interrupt requests are cleared when I = 1 in the CCR, IRQnSC = 0, and IRQnE = 0.
70
4.3.3
External Interrupts
The nine external interrupts are NMI and IRQ0 to IRQ7. NMI, IRQ 0 to IRQ2, and IRQ6 can be used to recover from software standby mode. NMI: A nonmaskable interrupt is generated on the rising or falling edge of the NMI input signal regardless of whether the I (interrupt mask) bit is set in the CCR. The valid edge is selected by the NMIEG bit in the system control register. The NMI vector number is 3. In the NMI hardware exception-handling sequence the I bit in the CCR is set to 1. IRQ0 to IRQ7: These interrupt signals are level-sensed or sensed on the falling edge of the input, as selected by ISCR bits IRQ0SC to IRQ7SC. These interrupts can be masked collectively by the I bit in the CCR, and can be enabled and disabled individually by setting and clearing bits IRQ0E to IRQ7E in the IRQ enable register. When one of these interrupts is accepted, the I bit is set to 1. IRQ0 to IRQ7 have interrupt vector numbers 4 to 11. They are prioritized in order from IRQ 7 (low) to IRQ0 (high). For details, see table 4.2. Interrupts IRQ 0 to IRQ7 do not depend on whether pins IRQ0 to IRQ7 are input or output pins. When using external interrupts IRQ0 to IRQ7, clear the corresponding DDR bits to 0 to set these pins to the input state, and do not use these pins as input or output pins for the timers, serial communication interface, or A/D converter. 4.3.4 Internal Interrupts
Thirty-three internal interrupts can be requested by the on-chip supporting modules. Each interrupt source has its own vector number, so the interrupt-handling routine does not have to determine which interrupt has occurred. All internal interrupts are masked when the I bit in the CCR is set to 1. When one of these interrupts is accepted, the I bit is set to 1 to mask further interrupts (except NMI). The vector numbers are 12 to 44. For the priority order, see table 4.2.
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4.3.5
Interrupt Handling
Interrupts are controlled by an interrupt controller that arbitrates between simultaneous interrupt requests, commands the CPU to start the hardware interrupt exception-handling sequence, and furnishes the necessary vector number. Figure 4.3 shows a block diagram of the interrupt controller.
NMI interrupt IRQ0 flag IRQ0E * IRQ0 interrupt Priority decision
Interrupt controller
CPU
Interrupt request
Vector number
ADF ADIE
ADI interrupt
I (CCR)
Note: * For edge-sensed interrupts, these AND gates change to the circuit shown below. IRQ0 edge IRQ0E IRQ0 flag S Q
IRQ0 interrupt
Figure 4.3 Block Diagram of Interrupt Controller The IRQ interrupts and interrupts from the on-chip supporting modules all have corresponding enable bits (except for the watchdog timer reset option). When the enable bit is cleared to 0, the interrupt signal is not sent to the interrupt controller, so the interrupt is ignored. These interrupts can also all be masked by setting the CPU's interrupt mask bit (I) to 1. Accordingly, these interrupts are accepted only when their enable bit is set to 1 and the I bit is cleared to 0.
72
The nonmaskable interrupt (NMI) is always accepted, except in the reset state and hardware standby mode. When an NMI or another enabled interrupt is requested, the interrupt controller transfers the interrupt request to the CPU and indicates the corresponding vector number. (When two or more interrupts are requested, the interrupt controller selects the vector number of the interrupt with the highest priority.) When notified of an interrupt request, at the end of the current instruction or current hardware exception-handling sequence, the CPU starts the hardware exception-handling sequence for the interrupt and latches the vector number. Figure 4.4 is a flowchart of the interrupt (and reset) operations. Figure 4.6 shows the interrupt timing sequence for the case in which the software interrupt-handling routine is in on-chip ROM and the stack is in on-chip RAM. 1. An interrupt request is sent to the interrupt controller when an NMI interrupt occurs, and when an interrupt occurs on an IRQ input line or in an on-chip supporting module provided the enable bit of that interrupt is set to 1. 2. The interrupt controller checks the I bit in the CCR and accepts the interrupt request if the I bit is cleared to 0. If the I bit is set to 1 only NMI requests are accepted; other interrupt requests remain pending. 3. Among all accepted interrupt requests, the interrupt controller selects the request with the highest priority and passes it to the CPU. Other interrupt requests remain pending. 4. When it receives the interrupt request, the CPU waits until completion of the current instruction or hardware exception-handling sequence, then starts the hardware exceptionhandling sequence for the interrupt and latches the interrupt vector number. 5. In the hardware exception-handling sequence, the CPU first pushes the PC and CCR onto the stack. See figure 4.5. The stacked PC indicates the address of the first instruction that will be executed on return from the software interrupt-handling routine. 6. Next the I bit in the CCR is set to 1, masking all further interrupts except NMI. 7. The vector address corresponding to the vector number is generated, the vector table entry at this vector address is loaded into the program counter, and execution branches to the software interrupt-handling routine at the address indicated by that entry.
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Program execution
Interrupt requested? Yes Yes NMI? No I = 0? Yes IRQ0? Yes No
No
No
Pending
No IRQ1? Yes OVF? Yes Latch vector no.
Save PC
Reset
Save CCR
I1
Read vector address
Branch to software interrupt-handling routine
Figure 4.4 Hardware Interrupt-Handling Sequence
74
SP - 4 SP - 3 SP - 2 SP - 1 SP (R7) Stack area
SP(R7) SP + 1 SP + 2 SP + 3 SP + 4
CCR CCR* PC (upper byte) PC (lower byte) Even address
Before interrupt is accepted
Pushed onto stack
After interrupt is accepted
PC: Program counter CCR: Condition code register SP: Stack pointer Notes: 1. The PC contains the address of the first instruction executed after return. 2. Registers must be saved and restored by word access at an even address. * Ignored on return.
Figure 4.5 Usage of Stack in Interrupt Handling Although the CCR consists of only one byte, it is treated as word data when pushed on the stack. In the hardware interrupt exception-handling sequence, two identical CCR bytes are pushed onto the stack to make a complete word. When popped from the stack by an RTE instruction, the CCR is loaded from the byte stored at the even address. The byte stored at the odd address is ignored.
75
Interrupt accepted Interrupt priority decision. Wait for Instruction Internal end of instruction. prefetch processing Interrupt request signal Vector fetch
Stack
Instruction prefetch (first instruction of Internal interrupt-handling process- routine) ing
o
Internal address bus
(1)
(3)
(5)
(6)
(8)
(9)
Internal read signal Internal write signal
Internal 16-bit data bus
(2)
(4)
(1)
(7)
(9)
(10)
Instruction prefetch address (Pushed on stack. Instruction is executed on return from interrupt-handling routine.) (2) (4) Instruction code (Not executed) (3) Instruction prefetch address (Not executed) (5) SP-2 (6) SP-4 (7) CCR (8) Address of vector table entry (9) Vector table entry (address of first instruction of interrupt-handling routine) (10) First instruction of interrupt-handling routine
(1)
Figure 4.6 Timing of Interrupt Sequence
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4.3.6
Interrupt Response Time
Table 4.4 indicates the number of states that elapse from an interrupt request signal until the first instruction of the software interrupt-handling routine is executed. Since on-chip memory is accessed 16 bits at a time, very fast interrupt service can be obtained by placing interrupt-handling routines in on-chip ROM and the stack in on-chip RAM. Table 4.4 Number of States before Interrupt Service
Number of States No. 1 2 3 4 5 6 Reason for Wait Interrupt priority decision Wait for completion of current instruction* 1 Save PC and CCR Fetch vector Fetch instruction Internal processing Total On-Chip Memory 2*
3
External Memory 2* 3 5 to 17* 2 12* 2 6* 2 12* 2 4 41 to 53* 2
1 to 13 4 2 4 4 17 to 29
Notes: 1. These values do not apply if the current instruction is EEPMOV. 2. If wait states are inserted in external memory access, add the number of wait states. 3. 1 for internal interrupts.
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4.3.7
Precaution
Note that the following type of contention can occur in interrupt handling. When software clears the enable bit of an interrupt to 0 to disable the interrupt, the interrupt becomes disabled after execution of the clearing instruction. If an enable bit is cleared by a BCLR or MOV instruction, for example, and the interrupt is requested during execution of that instruction, at the instant when the instruction ends the interrupt is still enabled, so after execution of the instruction, the hardware exception-handling sequence is executed for the interrupt. If a higher-priority interrupt is requested at the same time, however, the hardware exception-handling sequence is executed for the higher-priority interrupt and the interrupt that was disabled is ignored. Similar considerations apply when an interrupt request flag is cleared to 0. Figure 4.7 shows an example in which the OCIAE bit is cleared to 0.
CPU write cycle to TIER o Internal address bus TIER address
OCIA interrupt handling
Internal write signal OCIAE OCFA OCIA interrupt signal
Figure 4.7 Contention between Interrupt and Disabling Instruction The above contention does not occur if the enable bit or flag is cleared to 0 while the interrupt mask bit (I) is set to 1.
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4.4
Note on Stack Handling
In word access, the least significant bit of the address is always assumed to be 0. The stack is always accessed by word access. Care should be taken to keep an even value in the stack pointer (general register R7). Use the PUSH and POP (or MOV.W Rn, @-SP and MOV.W @SP+, Rn) instructions to push and pop registers on the stack. Setting the stack pointer to an odd value can cause programs to crash. Figure 4.8 shows an example of damage caused when the stack pointer contains an odd address.
PCH SP PCL
SP
R1L PCL
H'FECC H'FECD
SP
H'FECF
BSR instruction
MOV.B R1L, @-R7
H'FECF set in SP
PC is improperly stored beyond top of stack
PCH is lost
PCH: PCL: R1L: SP:
Upper byte of program counter Lower byte of program counter General register Stack pointer
Figure 4.8 Example of Damage Caused by Setting an Odd Address in R7
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Section 5 Data Transfer Unit
5.1 Overview
The H8/3318 Series has an on-chip data transfer unit (DTU) with four direct memory access (DMA) channels, and an on-chip 8-bit parallel buffer interface (PBI). When combined, these two functions enable up to 256 bytes of on-chip RAM to be easily accessed (read or write) from outside the chip. In I/O transfer, the DTU can perform data transfer automatically between on-chip RAM and registers of the serial communication interface (SCI), 16-bit free-running timer (FRT), programmable timing pattern controller (TPC), and A/D converter (ADC), in response to an interrupt request. In PBI transfer, the DTU can implement a large dual-port RAM (DPRAM) by enabling up to 256 bytes of on-chip RAM to be accessed from an external master CPU. In its DPRAM mode, the PBI has a buffer that can be queried to read one byte from a specified address. While accepting buffer queries, the PBI can also operate in bound buffer mode, which provides sequential read/write access starting from a specified address, or direct word mode, which does not use the DTU and on-chip RAM. The PBI can operate in handshake mode as well as DPRAM mode. 5.1.1 Features
Features of I/O transfer, DPRAM mode, and handshake mode are listed below. I/O Transfer (Figure 5.1) * The three DTU channels with I/O transfer capability (channels A, B, and C) can perform DMA independently. * The selectable types of transfer are: RAM to SCI (TDR), SCI (RDR) to RAM; RAM to FRT (OCRA, OCRB); RAM to TPC (NDR); and ADC (ADDRA) to RAM. * The number of bytes transferred can be controlled by setting a starting address and boundary. Each channel can generate an independent interrupt when the designated number of bytes have been transferred. * A maximum 256-byte RAM area can be used (maximum 128 bytes per channel). * Data in a specified area can be transferred repeatedly by designating repeat mode. * Channel B can be set to operate in ring buffer mode (FIFO mode).
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Supporting module Halted CPU I/O register Interrupt
DTU RAM Temporary data register*
Note: * Different from DPDRR and DPDRW
Figure 5.1 Concept of I/O Transfer DPRAM Mode * A master CPU can access on-chip RAM randomly via a buffer, by using DTU channel R as read DMA (buffer query). * The master CPU can access on-chip RAM sequentially via a pair of buffers, using DTU channel A for read DMA and channel B for write DMA (bound buffer mode). Without using the DTU, the master CPU can also access the buffers in each channel as a dual-port RAM (direct word mode). * A maximum 256-byte RAM area can be used (maximum 128 bytes each in channel A and B). * Internal CPU interrupts can be generated when the designated number of bytes have been transferred (master read end, master write end). * In single-chip mode, master CPU interrupt requests can be issued from the RDY pin, and wait requests from the WRQ pin. In the expanded modes, one of these two types of requests can be generated: master CPU interrupt requests can be issued from the RDY pin, or wait requests can be issued from the WRQ pin. Buffer query operation (Figure 5.2) * A 1-byte address/data register is available. By writing an on-chip RAM address, the master CPU can read any byte in a 256-byte on-chip RAM area.
82
RS0 to RS2 RAM DTU DPRAM data register (query read) Slave CPU Halted DDB0 to DDB7 WE OE CS WRQ
Figure 5.2 Concept of Buffer Queries Bound buffer mode (Figure 5.3) * Two pairs of 8-bit data registers are available, one for read and one for write. The master CPU can use these as buffers to transfer data to or from a 256-byte on-chip RAM area with no wait time. * The number of bytes to be transferred can be designated by setting a starting address and boundary. Each channel can generate an internal CPU interrupt when the designated number of bytes have been transferred. * In a read operation by the master CPU, data is transferred from addresses specified by the internal CPU. * In a write operation by the master CPU, data is transferred to addresses specified by the master CPU.
CS WE OE
DTU RAM DPRAM data register (write)
RS0 to RS2 CPU Halted DPRAM data register (read) DDB0 to DDB7 RDY WRQ
Figure 5.3 Concept of Bound Buffer Mode
83
Direct word mode (Figure 5.4) * Two pairs of 8-bit data registers are available, one for read and one for write. These can be used as a dual-port RAM to exchange data with the master CPU. Channels not using bound buffer mode are automatically placed in direct word mode.
DTU DPRAM data register (write) Slave CPU DPRAM data register (read) RS0 to RS2 DDB0 to DDB7 WE OE CS RDY
Figure 5.4 Concept of Direct Word Mode Handshake Mode (Figure 5.5) * Handshaking is carried out using OE and WE input signals and RDY and WRQ output signals. * An internal CPU interrupt can be generated at the rise of the OE input (output data processing completed) and rise of the WE input (input data valid). * The RDY and WRQ output signals can be used to send interrupt requests and data input/output requests to the master CPU.
DTU For reception DPRAM data register (write) Slave CPU For transmission DPRAM data register (read) WE WRQ DDB0 to DDB7
OE RDY
Figure 5.5 Concept of Handshake Mode
84
5.1.2
Block Diagram
Figure 5.6 shows a block diagram of the DTU and PBI.
Internal address bus
Bus request
Internal data bus
Internal data bus interface I/O control register (IOCR) Data transfer address register H (DTARH) Reload address register C (RLARC)
Data transfer address register C (DTARC) Data transfer control register C (DTCRC) Internal address bus interface, incrementer, and boundary decoder Reload address register B (RLARB)
Data transfer address register B (DTARB) Module master data bus
Comparator
DTU control circuit
Compare address register B (CPARB) Data transfer control register B (DTCRB) Reload address register A (RLARA)
Data transfer address register A (DTARA) Data transfer control register A (DTCRA) DPRAM data register read query (DPDRRQ) DPRAM data register write H (DPDRWH) DPRAM data register write L (DPDRWL) DPRAM data register read H (DPDRRH) OCIB OCIA ADI RXI TXI DPRAM data register read L (DPDRRL) Parallel communication control/status register (PCCSR) PBI control circuit DPRAM data bus interface DDB7 to DDB0
Figure 5.6 DTU and PBI Block Diagram
85
RS2 to RS0
WRQ
OE
RDY
WE
CS
Module data bus
5.1.3
Input and Output Pins
Table 5.1 lists the input and output pins. CS, OE, WE, RDY, and DDB are active only in single-chip mode. In expanded mode, XCS, XOE, XWE, XRDY, XDDB become active instead. Table 5.1
Name Chip select Register select Output enable Write enable Ready Wait request DPRAM data bus
Input and Output Pins
Abbreviation* 1 CS, XCS RS 2 to RS0 OE, XOE WE, XWE RDY, XRDY WRQ DDB7 to DDB 0 XDDB7 to XDDB 0 I/O Input Input Input Input Output Output Input/ output Function (DPRAM Mode) Selects the PBI Used by the master CPU to select a PBI register* 2 Used by the master CPU to read a PBI register Used by the master CPU to write to a PBI register Sends an interrupt request to the master CPU Sends a wait request to the master CPU 8-bit data bus providing a parallel interface between the master CPU and PBI
Notes: 1. Unless specifically noted, XCS, XOE, XWE, XRDY, and XDDB will be referred to as CS, OE, WE, RDY, and DDB, respectively. 2. The registers selected by the register select signals are listed in table 5.2.
86
5.1.4
Register Configuration
Table 5.2 lists the DTU and PBI registers Table 5.2 DTU and PBI Registers
Address
Name Parallel communication control/status register (PCCSR)
I/O control register DPRAM data register read query Data transfer address register H Data transfer control register A Data transfer address register A Reload address register A Data transfer control register B Data transfer address register B Reload address register B Compare address register B Data transfer control register C Data transfer address register C Reload address register C DPRAM data register write H DPRAM data register write L DPRAM data register read H DPRAM data register read L Serial/timer control register System control register
Abbreviation PCCSR
R/W R/W
Initial Value H'04
Internal H'FFF0
RS 2 to RS 0 Description 000 P95
IOCR DPDRRQ DTARH DTCRA DTARA RLARA DTCRB DTARB RLARB CPARB DTCRC DTARC RLARC DPDRWH DPDRWL DPDRRH DPDRRL STCR SYSCR
R/W -- R/W * * R * * R R/W R/W R/W -- * * * * R/W R/W
H'03 Undetermined Undetermined H'00 Undetermined Undetermined H'00 Undetermined Undetermined Undetermined H'00 Undetermined Undetermined Undetermined Undetermined Undetermined Undetermined H'1C H'09
H'FFF1 -- H'FFF5 H'FFF6 H'FFF7 H'FFF2 H'FFF8 H'FFF9 H'FFF3 H'FFF4 H'FFFA H'FFFB -- H'FFFC H'FFFD H'FFFE H'FFFF H'FFC3 H'FFC4
-- 001 -- 010 011 -- 010 011 -- -- -- -- -- 100 101 110 111 -- --
P84 P95 P89 P86 P89 P90 P86 P89 P90 P90 P86 P89 P90 P93 P93 P94 P94 P91 P99
Note: * Register read/write specifications are given in table 5.3, Transfer Modes and Register Configuration.
Register accessibility differs depending on the transfer mode. Table 5.3 lists the register access conditions for each transfer mode, and table 5.4 shows how each transfer mode is selected.
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Table 5.3
Transfer Modes and Register Configuration
R/W DPRAM Mode PBI Transfer I/O Transfer Buffer Query* 1 Master CPU R/W -- R/W -- -- -- --
3
Bound Buffer Mode Master CPU R/W -- x -- -- | R* 4 -- | R* 4 -- Internal CPU R/W R/W -- R/W x | R/W*5 x | R/W*5 | R* 5
4
Direct Word Mode Master CPU R/W -- x -- -- -- -- --|x*
4
Handshake Mode* 2 Internal Initial CPU Value R/W R/W -- x x x x x x x x -- R W H'04 H'03 * * H'00 * * H'00 * * * H'00 * * * * * *
Address RS 2 to Internal RS 0 H'FFF0 H'FFF1 -- H'FFF5 H'FFF6 H'FFF7 H'FFF2 H'FFF8 H'FFF9 H'FFF3 H'FFF4 H'FFFA H'FFFB -- 000 -- 001 -- 010 011 -- 010 011 -- -- -- -- --
Chan- Abbrenel viation PCCSR IOCR R DPDRRQ DTARH A DTCRA DTARA RLARA B DTCRB DTARB RLARB CPARB C DTCRC DTARC RLARC
Internal CPU x R/W -- R/W R/W | x * 3 R/W | x * 3 R| R/W | x *
Internal CPU R/W R/W -- x x x x
--|x*
4
-- | W*
x | R*
5
R/W | x * 3 R| R/W | x * 3 R/W R/W --
-- | x *4 -- -- -- -- -- x x x x
-- | W*4 -- -- -- -- -- W W R R
x | R* 5 | R*
5
-- | x *4 x -- -- -- -- -- x x x -- R R W W
x | R/W*5 x x
DPDRWH x DPDRWL DPDRRH DPDRRL x x x
-- --
W W R R
H'FFFC 100 H'FFFD 101 H'FFFE H'FFFF 110 111
Legend x: Must not be accessed (write access will affect operations of other functions). : Can be accessed, but has no effect on operation. --: Cannot be accessed. *: Undetermined Notes: 1. Buffer queries can be made in parallel with bound buffer mode and direct word mode. DTARH and IOCR are used in all these modes, so care is required in modifying their contents. 2. In handshake mode, the master CPU can write to DPDRWL. The internal CPU can output the DPDRRL contents to the master CPU. 3. Must not be accessed if used in bound buffer mode. 4. Cannot be accessed if used for I/O transfer. 5. Must not be accessed if used for I/O transfer.
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Table 5.4
Transfer Mode Selection
Basically, I/O transfer mode can be started for channels A, B, and C at any time by setting DTE to 1. However, channels A and B may be assigned for transfer in bound buffer mode, depending on the IOCR setting. (See table 5.5 and section 5.3.3.)
I/O transfer mode
DPRAM mode Buffer queries Channel R is used exclusively. The buffer query function operates when DPME = 1 in SYSCR and HSCE = 0 in IOCR. (See table 5.5 and section 5.3.4.) Channel A is used for reads to the master. This mode can be used when DPME = 1 (SYSCR), HSCE = 0 (IOCR), and DPEA = 1 (IOCR). Channel B is used for writes from the master. This mode can be used when DPME = 1 (SYSCR), HSCE = 0 (IOCR), and DPEB = 1 (IOCR). (See table 5.5 and section 5.3.5.) Channel A is used for reads to the master. This mode can be used when DPME = 1 (SYSCR), HSCE = 0 (IOCR), and DPEA = 0 (IOCR). Channel B is used for writes from the master. This mode can be used when DPME = 1 (SYSCR), HSCE = 0 (IOCR), and DPEB = 0 (IOCR). (See table 5.5 and section 5.3.6.) This mode can be used when DPME = 1 in SYSCR and HSCE = 1 in IOCR. (See table 5.5 and section 5.3.7.)
Bound buffer mode
Direct word mode
Handshake mode
5.2
Register Descriptions
The registers of the DTU and PBI are described below. Abbreviations shown in boxes after the register name indicate the modes in which the register can be used. The meaning of these abbreviations is as follows: I/O: Q: BB: DI: H/S: I/O transfer Buffer queries Bound buffer mode Direct word mode Handshake mode
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5.2.1
I/O Control Register (IOCR)
I/O Q BB DI H/S
Bit
7 HSCE
6 DPEA 0 R/W
5 DPEB 0 R/W
4 RPEA 0 R/W
3 RPEB 0 R/W
2 RPEC 0 R/W
1 -- 1 --
0 -- 1 --
Initial value Read/Write
0 R/W
IOCR selects DTU and PBI operating modes, and controls the DTU. Bit 7--Parallel Handshake Enable (HSCE) Bits 6 and 5--DPRAM Enable A and B (DPEA, DPEB) The DTU and PBI operating modes are selected by the DPME bit in SYSCR, and the HSCE, DPEA, and DPEB bits in IOCR. Table 5.5 lists the mode selections. Table 5.6 lists the corresponding pin functions. Table 5.5 DTU/PBI Operating Mode Settings
Bound Buffer Mode (DTU Channel A) Bound Buffer Mode (DTU Channel B)
Buffer Query Hand- (DTU DPME Bit 7 Bit 6 Bit 5 shake Channel (SYSCR) HSCE DPEA DPEB Mode R) 1 1 0 -- 0 1 0 1 0 -- -- -- 0 0 1 1 -- O x x x x x x O (read) O (read) O (read) O (read) x
Direct Word Mode (DPDRRH/L)
Direct Word Mode (DPDRWH/L) Handshake O (write)
I/O transfer* I/O transfer* Handshake I/O transfer* I/O transfer* O (read) O (read)
I/O transfer* Bound buffer O (write) O (read) Bound buffer
I/O transfer* O (write) O (read) O (write)
Bound buffer Bound buffer x
I/O transfer* I/O transfer* x
O: x: --: *:
Can be used Cannot be used Undetermined Used in I/O transfer mode
Note: For I/O transfer, set the DTE bit to 1 in DTCRA, DTCRB, or DTCRC. Handshake mode operation is supported only in single-chip mode. Do not set bit HSCE to 1 in expanded modes.
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Table 5.6
DPME
Pin Functions
Bit 7 HSCE Mode Name CS/XCS, RS2 to RS0 OE/XOE, WE/XWE Control input RDY/ XRDY Control output WRQ Control output or port function, depending on EWRQ (PCCSR) bit Port function Port function Port function Port function or data bus DDB7 to DDB0/ XDDB 7 to XDDB0 Data input/output
(SYSCR) 1
1
Handshake
mode DPRAM mode --
Port
function Control input Port function
0 0 --
Note: "Port function" means that the port functions, supporting-module functions, and extended functions multiplexed with the DPRAM pins are available.
Bits 4, 3, and 2--Repeat Enable A, B, and C (RPEA, RPEB, RPEC): These bits are valid only in I/O transfers. They select repeat mode or normal mode for DTU channels A, B, and C. In normal mode, the DTE bit in DTCRA, DTCRB, or DTCRC is cleared to 0 when the transfer reaches the boundary. In repeat mode, when the transfer reaches the boundary, the DTE bit in DTCRA, DTCRB, or DTCRC is not cleared to 0, and the data in the area defined by DTARA, DTARB, or DTARC and the boundary is transferred repeatedly. Channels A and B also have reload address registers, and channel B can furthermore operate in ring buffer mode. For usage of the boundary, normal mode, and repeat mode, see section 5.3, Operation.
Bits 4, 3, or 2 RPEA, B, C 0 1 Description Transfer in normal mode Transfer in repeat mode (Initial value)
Bits 1 and 0--Reserved: These bits cannot be modified and are always read as 1.
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5.2.2
Data Transfer Control Registers A, B, and C (DTCRA, DTCRB, DTCRC)
I/O BB
Bit
7
6
5
4
3
2
1
0
DTE DTIE BUD2 BUD1 BUD0 SOS2 SOS1 SOS0 Initial value Mode I/O transfer Register DTCRA DTCRB DTCRC DTCRA Internal CPU Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0
PBI transfer in DPRAM bound buffer mode
Internal CPU Master CPU
Read/Write Read/Write Read/Write Read/Write
0 0 0 --
(R/W) R/W R 0 -- R R W
R/W R R W
R/W (R/W) (R/W) (R/W) R R W R 0 -- R 0 -- R 0 --
DTCRB
Internal CPU Master CPU
--: Not used. Cannot be modified. 0: Always reads 0. (R/W): Can be written, but has no effect on operation.
These registers are used in I/O transfers, and in PBI transfers in DPRAM bound buffer mode. In I/O transfers, DTCRA, DTCRB, and DTCRC serve as control registers for DTU channels A, B, and C, respectively. In PBI transfers in DPRAM bound buffer mode, DTCRA controls read access by the master CPU, and DTCRB controls write access by the master CPU. Bit 7--Data Transfer Enable (DTE): Used in I/O transfers. Not used in PBI transfers. When DTE is set to 1, the channel begins waiting for a transfer request. The DMA transfer is activated by the interrupt request signal selected by the source select bits (SOS2, SOS1, SOS0). If a boundary overflow or the internal CPU clears the DTE bit to 0, the transfer is suspended. If the DTIE bit is set to 1, an interrupt is also requested. If the internal CPU sets the DTE bit to 1 again, the transfer resumes from the state in which it was suspended.
92
Bit 7 DTE 0
Description Indicates that I/O transfer is halted [Clearing conditions] 1. 0 is written in DTE 2. The transfer terminates at the boundary in normal mode (Initial value)
1
Indicates that I/O transfer is in progress [Setting condition] Read DTCR while DTE = 0, then write 1 in DTE
Bit 6--Data Transfer Interrupt Enable (DTIE): Used in I/O transfers. Not used in PBI transfers. This bit enables or disables the interrupt generated when the DTE bit is cleared to 0.
Bit 6 DTIE 0 1 Description Disables the interrupt requested when the DTE bit is cleared to 0 (DTI) Enables the interrupt requested when the DTE bit is cleared to 0 (DTI) (Initial value)
Bits 5, 4, and 3--Boundary 2, 1, and 0 (BUD2, BUD1, BUD0): These bits set a carry-control boundary in the data transfer address register (DTAR), which is the register that gives the lower byte of an on-chip RAM address. DTAR is an 8-bit counter that increments each time one byte or one word is transferred. The incrementing is held within the selected boundary. When a carry occurs at the boundary, causing a DTAR overflow, the bits above the boundary retain their existing values, while the bits below the boundary are reset to their initial value. The initial value may be 0, or a value stored in a reload register, depending on the channel and operating mode.
93
BUD2 BUD1 BUD0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
DTAR Overflow Timing End of each byte transfer Carry from bit 0 to bit 1 in DTAR Carry from bit 1 to bit 2 in DTAR Carry from bit 2 to bit 3 in DTAR Carry from bit 3 to bit 4 in DTAR Carry from bit 4 to bit 5 in DTAR Carry from bit 5 to bit 6 in DTAR Carry from bit 6 to bit 7 in DTAR
Maximum Bytes Transferred* 1 2 4 8 16 32 64 128
DTAR 7 6 5 4 3 2 1 0
Note: * Number of bytes transferred when bits below the boundary are initially cleared to 0.
Figure 5.7 Bit Settings and Boundary Positions Bits 2, 1, and 0--Source Select 2, 1, and 0 (SOS2, SOS1, SOS0): Used in I/O transfers, but not in PBI transfers. These bits select the interrupt source that activates an I/O transfer by the DTU. When DTE is set to 1, the selected interrupt request signal is regarded as an I/O transfer request. When DTE is 0, the selected interrupt request signal is sent to the interrupt controller. Table 5.7 lists the I/O transfer activation sources and the transfers they request. Some transfers clear the activation source while others do not. By using a combination of these types, it is possible to perform two consecutive transfer operations with a single activation source. In this case, the I/O transfers are performed in alphabetical channel order (channel A, then B, then C). If channel A or channel B executes transfer operation number 9 or 10 in table 5.7, the activation source is not cleared, and the channel is stopped. A stopped channel is automatically cleared by the completion of transfer operation 5 or 7 for stoppage due to transfer operation 9, or by completion of operation 4 or 6 for operation 10. A stopped channel can also be cleared by a dummy write to its data transfer control register (DTCR).
94
Table 5.7
Selection of Activation Sources and Resulting Transfers
Clearing DTU (Channel A) of Source SOS2 SOS1 SOS0 Yes Yes 0 0 0 0 1 1 1 0 1 DTU (Channel B) SOS2 SOS1 SOS0 0 0 0 0 1 1 1 0 1 DTU (Channel C) SOS2 SOS1 SOS0 0 0 0 1 1 0 0 1 1 1 1 1 1 0 0 1 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1
Interrupt No. Source Module Transfer 1 2 3 4 5 6 7 8 9 10 RXI0 TXI0 ADI OCIB1 OCIA1 OCIB1 OCIA1 OCIA1 OCIA1 OCIB1 SCI0 SCI0 ADC TPC TPC TPC TPC FRT1 FRT1 FRT1 RDR RAM (byte) RAM TDR (byte)
ADDRA RAM (word) Yes RAM NDRB (word) Yes RAM NDRB (word) Yes RAM NDRA (byte) RAM NDRA (byte) Yes Yes
RAM OCRA (word) Yes RAM OCRA (word) No RAM OCRB (word) No
Note: When SOS2 = SOS1 = SOS0 = 0, an activation source is not selected.
5.2.3
Data Transfer Address Register H (DTARH)
I/O Q BB
Bit
7
6
5
4
3
2
1
0
Initial value Read/Write
-- R/W
-- R/W
-- R/W
-- R/W
-- R/W
-- R/W
-- R/W
-- R/W
DTARH is used whenever the DTU function is used. It is used both for I/O transfers and for PBI transfers in DPRAM mode, including buffer queries and transfers in bound buffer mode. DTARH is the register that specifies the upper 8 bits of the on-chip RAM address. DTARH can be paired with DTARA, DTARB, or DTARC to generate a 16-bit address.
95
5.2.4
Data Transfer Address Registers A, B, and C (DTARA, DTARB, DTARC)
I/O Q BB
Bit
7
6
5
4
3
2
1
0
Initial value Mode I/O transfer Register DTARA DTARB DTARC DTARA Internal CPU Read/Write
--
--
--
--
--
--
--
--
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PBI transfer in DPRAM bound buffer mode
Internal CPU Master CPU
Read/Write Read/Write Read/Write Read/Write
R/W R R W
R/W R R W
R/W R R W
R/W R R W
R/W (R/W) (R/W) (R/W) R R W R R W R R W R R W
DTARB
Internal CPU Master CPU
The DTAR registers are used when the DTU function is used for I/O transfers, and for PBI transfers in DPRAM bound buffer mode. DTARA, DTARB, and DTARC pair with DTARH to generate 16-bit on-chip RAM addresses which indicate DTU transfer addresses. A boundary can be set in the DTAR registers by the BUD bits, so that the DTAR registers increment only in the range up to the boundary. In an I/O transfer, these registers are used as the lower 8-bit address registers in each channel. In a PBI transfer in DPRAM bound buffer mode, DTARA is the lower 8-bit address register in read access by the master CPU, and DTARB is the lower 8-bit address register in write access by the master CPU.
96
5.2.5
Reload Address Registers A, B, and C (RLARA, RLARB, RLARC)
I/O BB
Bit
7
6
5
4
3
2
1
0
Initial value Read/Write
-- R/W
-- R/W
-- R/W
-- R/W
-- R/W
-- R/W
-- R/W
-- R/W
The RLAR registers are used when the DTU function is used for I/O transfers, and for PBI transfers in DPRAM bound buffer mode. The RLAR registers store data for initializing the DTAR registers when a boundary overflow occurs. Writes to the RLAR registers are performed automatically by master CPU or internal CPU writes. The DTAR value is then successively incremented, and if a boundary overflow occurs, the DTAR register will be initialized to the value in the RLAR register. In ring buffer mode, RLARB functions as an auxiliary ring buffer pointer. DTARB is the main pointer, indicating the DTU transfer address. If a series of transfers is suspended and the stored data becomes invalid, DTARB can be initialized to the value in RLARB (loading). If a series of transfers ends normally and the stored data is valid, the contents of DTARB can be copied to RLARB (marking). Note, however, that in repeat mode the value in RLARB is copied to DTARB automatically when a boundary overflow occurs. 5.2.6 Compare Address Register B (CPARB)
BB
Bit
7
6
5
4
3
2
1
0
Initial value Read/Write
-- R/W
-- R/W
-- R/W
-- R/W
-- R/W
-- R/W
-- R/W
-- R/W
CPARB is an auxiliary pointer used in ring buffer mode. The contents of CPARB are constantly compared with DTARB. When they match, an interrupt request can be generated. CPARB should be updated by software so that it always indicates the top of the unprocessed data in the ring buffer. Then if the ring buffer becomes full of unprocessed data, causing an overrun error, CPARB and DTARB will match and an interrupt request will occur.
97
5.2.7
Serial/Timer Control Register (STCR)
BB
Bit
7 RING
6 CMPF 0 R/(W)*
5 CMPIE 0 R/W
4 LOAD 1 (W)
3 MARK 1 (W)
2 -- 1 --
1 ICKS1 0 R/W
0 ICKS0 0 R/W
Initial value Read/Write
0 R/W
Note: * Software can write a 0 in bit 6 to clear the flag, but cannot write a 1 in this bit.
STCR is an 8-bit readable/writable register that controls DTU channel B, and selects the SCI operating mode and the TCNT clock source. STCR is initialized to H'1C by a reset. Bit 7--Ring Buffer Mode (RING): Setting this bit to 1 places DTU channel B in ring buffer mode. To use ring buffer mode it is also necessary to set the REPB bit to 1 in IOCR.
Bit 7 RING 0 1 Description DTU channel B does not operate in ring buffer mode DTU channel B operates in ring buffer mode (Initial value)
Bit 6--Compare Interrupt Flag (CMPF): Overrun error interrupt request flag for the ring buffer. This flag indicates that the contents of CPARB and DTARB match after DTARB was incremented due to the occurrence of a DTU cycle.
Bit 6 CMPF 0 Description [Clearing condition] Read STCR while CMPF = 1, then write 0 in CMPF 1 Ring buffer overrun error [Setting condition] When DTARB contents match CPARB contents after being incremented by DTU cycle occurrence (Initial value)
Bit 5--Compare Interrupt Enable (CMPIE): Enables or disables the interrupt (CMPI) requested when CMPF is set to 1.
98
Bit 5 CMPIE 0 1
Description Interrupt request (CMPI) by CMPF is disabled Interrupt request (CMPI) by CMPF is enabled (Initial value)
Bit 4--Pointer Load (LOAD): Controls the copying of the contents of the auxiliary pointer (RLARB) into the ring buffer pointer (DTARB). There is no latch to retain the value of the LOAD bit. The load operation is executed when the LOAD bit is cleared to 0.
Bit 4 LOAD Cleared to 0 Set to 1 Description RLARB contents are copied to DTARB No operation (Initial value)
Bit 3--Pointer Mark (MARK): Controls the copying of the contents of the ring buffer pointer (DTARB) into the auxiliary pointer (RLARB). There is no latch to retain the value of the MARK bit. The mark operation is executed when the MARK bit is cleared to 0.
Bit 3 MARK Cleared to 0 Set to 1 Description DTARB contents are copied to RLARB No operation (Initial value)
Bit 2--Reserved: This bit cannot be modified and is always read as 1. Bits 1 and 0--Internal Clock Source Select 1 and 0 (ICKS1 and ICKS0): These bits, together with bits CKS2 to CKS0 in TCR, select the TCNT clock source. For details see section 11, 8-Bit Timers. 5.2.8 DPRAM Data Registers (DPDRWH, DPDRWL, DPDRRH, DPDRRL)
BB DI H/S
The DPRAM data registers (DPDR registers) provide four bytes, of which the master CPU can write to two bytes (DPDRW) and read two bytes (DPDRR). These data registers are used in DPRAM bound buffer mode, DPRAM direct word mode, and handshake mode. They are not used for buffer queries in DPRAM mode, or for I/O transfers. Read and write access to the DPDR registers sets interrupt flags (MWEF, MREF), activates the DTU, and changes the levels of control signals (RDY, WRQ) sent to the master CPU. For details of these operations, see section 5.3, Operation.
99
DPRAM Data Register Write H and L (DPDRWH, DPDRWL): These data registers are reserved for write access by the master CPU in DPRAM bound buffer mode, DPRAM direct word mode, and handshake mode. They are not used for buffer queries in DPRAM mode, or for I/O transfers.
Bit 7 6 5 4 3 2 1 0
Initial value Mode Register Internal CPU Master CPU Internal CPU Master CPU Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write
--
--
--
--
--
--
--
--
DRAM bound DPDRWH buffr mode DPDRWL DRAM direct word mode Handshake mode DPDRWH DPDRWL
R*1 W R W R W*
2
R*1 W R W R W*
2
R*1 W R W R W*
2
R*1 W R W R W*
2
R*1 W R W R W*
2
R*1 W R W R W*
2
R*1 W R W R W*
2
R*1 W R W R W*2
DPDRWL*3 Internal CPU Master CPU
Notes: 1. Transferred to on-chip RAM automatically by the DTU. 2. Data on the DDB lines is latched at the rising edge of the WE input. 3. In handshake mode, the master CPU cannot access DPDRWH.
The two DPDRW bytes should be used in each mode as follows. * DPRAM Bound Buffer Mode DPDRWH and DPDRWL are reserved for write access by the master CPU. Data written in these registers is transferred automatically to the on-chip RAM. The master CPU has two addresses for these two bytes, but write access to both bytes operates in the same way. * DPRAM Direct Word Mode Read or write access to DPDRWL generates an interrupt request to the internal CPU or master CPU. If both bytes are used, read or write access should be performed to DPDRWH first, then DPDRWL. If only one byte is used, use DPDRWL. * Handshake Mode Use DPDRWL.
100
DPRAM Data Register Read H and L (DPDRRH, DPDRRL): These data registers are reserved for read access by the master CPU in DPRAM bound buffer mode, DPRAM direct word mode, and handshake mode. They are not used for buffer queries in DPRAM mode, or for I/O transfers.
Bit 7 6 5 4 3 2 1 0
Initial value Mode Register Internal CPU Master CPU Internal CPU Master CPU
3
--
--
--
--
--
--
--
--
DRAM bound DPDRRH buffr mode DPDRRL DRAM direct word mode Handshake mode DPDRRH DPDRRL DPDRRL*
Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write
W*1 R W R W R*
2
W*1 R W R W R*
2
W*1 R W R W R*
2
W*1 R W R W R*
2
W*1 R W R W R*
2
W*1 R W R W R*
2
W*1 R W R W R*
2
W*1 R W R W R*2
Internal CPU Master CPU
Notes: 1. Transferred from on-chip RAM automatically by the DTU. 2. Data is output on the DDB lines when the OE input is low. 3. In handshake mode, the master CPU cannot access DPDRRH.
The two DPDRR bytes should be used in each mode as follows. * DPRAM Bound Buffer Mode DPDRRH and DPDRRL are reserved for read access by the master CPU. The read data is transferred automatically from on-chip RAM. The master CPU has two addresses for these two bytes, but read access to both bytes operates in the same way. * DPRAM Direct Word Mode Read or write access to DPDRRL generates an interrupt request to the internal CPU or master CPU. If both bytes are used, DPDRRH should be accessed first, then DPDRRL. If only one byte is used, use DPDRRL. * Handshake Mode Use DPDRRL.
101
5.2.9
DPRAM Data Register Read Query (DPDRRQ)
This register is used as a query buffer in DPRAM mode.
Q
Bit
7
6
5
4
3
2
1
0
Initial value Internal CPU Master CPU Read/Write Read/Write
-- W* R/W
-- W* R/W
-- W* R/W
-- W* R/W
-- W* R/W
-- W* R/W
-- W* R/W
-- W* R/W
Note: * Transferred automatically from on-chip RAM by the DTU.
DPDRRQ is reserved for read and write access by the master CPU. When a write access to DPDRRQ occurs, data stored in on-chip RAM at the address given by DTARH (upper byte) and DPDRRQ (lower byte) is transferred to DPDRRQ. 5.2.10 Parallel Communication Control/Status Register (PCCSR)
Q BB DI H/S
This register is used in DPRAM mode and handshake mode. It is not used in I/O transfers. PCCSR can be written and read by both the internal CPU and the master CPU. It controls data transfer between the internal CPU and master CPU, and indicates status.
Bit 7 6 5 4 3 2 1 0 EMRI 0
QREF EWRQ Initial value Mode All modes except handshake mode Handshake mode Internal CPU Master CPU Internal CPU Read/Write Read/Write Read/Write R R R R R/W R/W 0 0
EWAKAR ERAKAR
MWEF MREF EMWI 0 0 0
0
0
R R/W R/W
R R/W R/W
R/(W)* R/(W)* R R
R/W R R/W
R/W R R/W
R/(W)* R/(W)*
Note: * Only 0 write after read is available.
102
Bit 7--Query Read End Flag (QREF): Indicates whether DPDRRQ contains an on-chip RAM address or data. This flag is useful in buffer query operations in DPRAM mode.
Bit 7 QREF 0 Description DPDRRQ contains data [Clearing condition] The DTU writes on-chip RAM data in DPDRRQ 1 DPDRRQ contains the lower byte of an on-chip RAM address [Setting condition] The master CPU writes the lower byte of an on-chip RAM address in DPDRRQ (Initial value)
Bit 6--Enable Wait Request (EWRQ): Enables operation of the WRQ pin. Bit 5--Enable Write Acknowledge and Request (EWAKAR): Enables operation of the RDY pin in response to master write access. Bit 4--Enable Read Acknowledge and Request (ERAKAR): Enables operation of the RDY pin in response to master read access. Table 5.8 lists the pin states in single-chip mode. Table 5.9 lists the pin states in the expanded modes.
103
Table 5.8
Condition DPME = 1, HSCE = 0
Pin States in Single-Chip Mode with PCCSR Conditions
Bit 6 EWRQ * * * * 0 1 Bit 5 EWAKAR 0 1 0 1 * * * * Bit 4 ERAKAR 0 0 1 1 * * * * P95/RDY High level output (high impedance) RDY output enabled at master write RDY output enabled at master read RDY output enabled at master write and master read Depends on value of ERAKAR and EWAKAR as above RDY output enabled RDY output enabled Port function WRQ output enabled Port function WRQ output enabled P83/WRQ/XRDY Depends on value of EWRQ as below
DPME = 1, HSCE = 1
0 1
Table 5.9
Condition DPME = 1, HSCE = 0
Pin States in Expanded Modes with PCCSR Conditions
Bit 6 EWRQ 0 0 0 0 1 Bit 5 EWAKAR 0 1 0 1 * * * Bit 4 ERAKAR 0 0 1 1 * * * P95/RDY AS output AS output AS output AS output AS output AS output AS output P83/WRQ/XRDY High level output XRDY output enabled at master write XRDY output enabled at master read XRDY output enabled at master write and master read WRQ output enabled XRDY output enabled WRQ output enabled
DPME = 1, HSCE = 1
0 1
104
Table 5.10 describes RDY output operations. Table 5.11 describes WRQ operations. Table 5.10 RDY Output Operations
Mode DPRAM bound buffer mode DPRAM direct word mode Handshake mode Master read Master write Master read Master write Conditions for High Level Output* Master CPU reads DTARA Master CPU writes to DTARB Master CPU reads DPDRRL Conditions for Low Level Output Internal CPU clears MREF Internal CPU clears MWEF Internal CPU writes to DPDRRL OE is high and WE is low
Master CPU writes to DPDRWL Internal CPU reads DPDRWL Internal CPU reads DPDRWL
Note: * During single-chip mode, pin RDY becomes an NMOS open drain output pin. High level output at this time refers to the high impedance state.
Table 5.11 WRQ Output Operations
Mode DPRAM bound buffer mode Master read Master write Conditions for High Level Output DTU completes transfer to DPDRRH/L DTU completes transfer from DPDRWH/L DTU completes transfer to DPDRRQ 8 system clocks after OE and WRQ both become low Conditions for Low Level Output Master CPU reads DPDRRH/L before DTU transfers new data Master CPU writes to DPDRWH/L before DTU transfers old data Master CPU reads DPDRRQ before DTU transfers new data Internal CPU writes to DPDRRL
Buffer query in DPRAM mode Handshake mode
105
Bit 3--Master Write End Flag (MWEF) Bit 2--Master Read End Flag (MREF) Table 5.12 describes the operation of MREF and MWEF. Table 5.13 explains the meaning of MREF and MWEF. Table 5.12 MREF and MWEF Operations
Mode DPRAM bound buffer mode MREF MWEF DPRAM direct word mode MREF MWEF Handshake mode MREF MWEF Clearing Condition Internal CPU reads MREF = 1, then writes 0 in MREF Internal CPU reads MWEF = 1, then writes 0 in MWEF Internal CPU writes to or dummy-reads DPDRRL Internal CPU reads or dummy-writes to DPDRWL Internal CPU writes to or dummy-reads DPDRRL Internal CPU reads or dummy-writes to DPDRWL Setting Condition DTU channel A has completed transfer up to boundary DTU channel B has completed transfer up to boundary Master CPU reads DPDRRL Master CPU writes to DPDRWL OE goes high WE goes high
Table 5.13 Meaning of MREF and MWEF
Mode DPRAM bound buffer and direct word modes MREF 0 Internal CPU has finished preparing data to be read by master CPU Internal CPU has finished processing data written by master CPU Internal CPU has prepared data to be output to master CPU Internal CPU has read data latched by master CPU 1 Master CPU has finished reading data prepared by internal CPU Master CPU has finished writing data to be processed by internal CPU Master CPU has read data being output by internal CPU Master CPU has caused internal CPU to latch data
MWEF
Handshake mode
MREF MWEF
106
Bit 1--Enable Master Write Interrupt (EMWI): Enables or disables the interrupt (MWEI) requested by MWEF when MWEF is set to 1.
Bit 1 EMWI 0 1 Description Disables interrupt request (MWEI) by MWEF Enables interrupt request (MWEI) by MWEF (Initial value)
Bit 0--Enable Master Read Interrupt (EMRI): Enables or disables the interrupt (MREI) requested by MREF when MREF is set to 1.
Bit 0 EMRI 0 1 Description Disables interrupt request (MREI) by MREF Enables interrupt request (MREI) by MREF (Initial value)
5.2.11
Bit
System Control Register (SYSCR)
7 SSBY 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 XRST 1 R 2 NMIEG 0 R/W 1 DPME 0 R/W 0 RAME 1 R/W
Initial value Read/Write
0 R/W
Bit 1--DPRAM Enable Bit (DPME): Selects whether to put the chip into slave mode. When using a transfer mode other than I/O transfer, the chip must be put into slave mode. See tables 5.5 and 5.6. DPME is initialized at reset and in hardware standby mode.
Bit 1 DPME 0 1 Description The chip is not put into slave mode The chip is put into slave mode (Initial value)
For descriptions of other bits of SYSCR, refer to section 3.2, System Control Register.
107
5.3
5.3.1
Operation
DTU Operation
DTU Operation Overview: The DTU operates by sharing the CPU's data bus, address bus, and bus control signals. To carry out a transfer, the DTU gets the bus right and generates a DTU bus cycle. During the DTU bus cycle, CPU bus cycles are held pending, while internal CPU operations can proceed concurrently. A DTU bus cycle is initiated by a DTU bus request. In case of contention between CPU and DTU bus cycle requests, the DTU bus cycle has priority. A request for a DTU bus cycle can occur at the end of a CPU bus cycle or DTU bus cycle. When the CPU is operating internally or in sleep mode, a request can occur at any time. A DTU bus cycle bus request is generated in response to a transfer request. The source of the transfer request may be an interrupt request from an on-chip supporting module, or a low-to-high transition at the OE or WE pin in the PBI. These transfer requests are recognized when the CPU is active or in sleep mode, but are not recognized in the reset state or standby modes. Types of DTU Bus Cycles: Table 5.14 classifies the bus cycles generated by the DTU and indicates their transfer request sources. A DPRAM cycle occurs when the DTU acquires the bus right for a PBI transfer request. There are two types of DPRAM cycles: master read, and master write. DTU channels R and A can generate master read cycles. DTU channel B can generate master write cycles. Dead cycles, read cycles, and write cycles occur when the DTU acquires the bus right for an I/O transfer request. I/O transfers can be carried out on three DTU channels: channels A, B, and C. Each channel executes a series of DTU bus cycles consisting of a dead cycle, read cycle, and write cycle.
108
Table 5.14 Types of DTU Bus Cycles
Type PBI transfer cycle Name Master read cycle Master write cycle I/O transfer cycle Dead cycle Read cycle Write cycle Operation Read on-chip RAM and simultaneously input data to PBI Output data from PBI and simultaneously write to on-chip RAM Confirmation of transfer request Read on-chip RAM or register of on-chip supporting module Write to on-chip RAM or register of on-chip supporting module Request Source PBI PBI Supporting module DTU DTU
DTU Bus Cycle Processing: Data is transferred from on-chip RAM to the PBI in a master read cycle, or from the PBI to on-chip RAM in a master write cycle. A dead cycle is a one-state waiting interval to be certain of a transfer request. During a DTU bus cycle after the dead cycle, the transfer request cannot be cancelled by the CPU. During the dead cycle, the flag of the free-running timer (FRT) or A/D converter, the source of the transfer request, is cleared. Data is transferred from on-chip RAM or an on-chip supporting module to the DTU in a read cycle, and from the DTU to on-chip RAM or an on-chip supporting module in a write cycle. Interrupt flags in the SCI are cleared automatically when the receive data register is read or when data is written in the transmit data register. Canceling an I/O Transfer Request: I/O transfer requests are generated by interrupt flags in the on-chip supporting modules. If the CPU clears the interrupt flag, the transfer request will be cancelled. If the transfer request is cancelled during a dead cycle, the following read cycle and write cycle will not be executed. Priority of Transfer Requests and Bus Requests: Table 5.15 indicates the priority order of transfer requests. A transfer request for a master read cycle caused by a buffer query in DPRAM mode always has highest priority. Among transfer requests in DPRAM bound buffer mode, master read has priority over master write. I/O transfers are basically performed in alphabetical order of channels (A,B,C), but in some cases a bus request will not be generated even though a transfer request is present. No bus request is generated for a one-state interval (dead cycle) after a write cycle. PBI transfers take priority over I/O transfers, so a PBI transfer may be inserted during the execution of a series of I/O transfer cycles. If there is a PBI transfer request at the end of a read cycle, the write cycle will be held pending until all PBI transfer processing is completed.
109
Table 5.15 Priority Order of DTU Transfer Requests
Priority of DTU Bus Cycle Activation Master Read Cycle (Ch. R) 1 1 Master Read Cycle (Ch. A) 2 2 Master Write Cycle (Ch. B) 3 3 Pending Write Cycle 4 --
Preceding Operation Other than below Dead cycle of cancelled bus request Dead cycle Read cycle Write cycle
Dead Cycle 5 4
Read Cycle -- --
Write Cycle -- --
-- 1 1
-- 2 2
-- 3 3
-- -- --
1 -- --
-- 4* --
-- -- --
Notes: Master read cycle in channel R: buffer query in DPRAM mode Master read cycle in channel A: DPRAM bound buffer mode Dead cycle priority order: channel A, channel B, channel C * Write cycle only in the channel that generated the preceding read cycle. Held pending if a higher-priority PBI transfer cycle is executed.
Address Bus Operations: Figure 5.8 shows a conceptual diagram of the DTU address-bus circuits. The DTARH contents, or H'FF, are output on the upper 8 bits of the 16-bit address bus. The contents of DTARA, DTARB, DTARC, or DPDRRQ, or the address of a supporting-module register determined by an I/O transfer request source, are output on the lower 8 bits.
110
DTARH H'FF
Address bus, upper 8 bits
Incrementer
RLARA
DTARA Internal bus
RLARB
DTARB
Channel select
Comparator
Lower address select
CPARB
DTARC
RLARC
DPDRRQ DTCRA SOS2 to SOS0 DTCRB SOS2 to SOS0 DTCRC SOS2 to SOS0 SOS decoder A SOS decoder B SOS decoder C Channel select
Figure 5.8 Concept of Address Bus Circuits
111
Address bus, lower 8 bits
Upper address select
Data Bus Operations: Figure 5.9 shows a conceptual diagram of the DTU data-bus circuits. The DTU temporary data registers (DTDRH/L) are connected to a 16-bit data bus. Data is read into the DTDR registers in a read cycle, and written out from the DTDR registers in a write cycle. The PBI data registers (DPDR) are connected to an 8-bit data bus. Data is read into DPDRRQ or DPDRRH/L in a master read cycle, and written out from DPDRWH/L in a master write cycle.
DTDRL [Module master data bus] DPDRRQ DPDRRH Select DPDRRL DPDRWH Select DPDRWL Select Select
Figure 5.9 Concept of Data Bus Circuits Table 5.16 Bus Operation in DTU Bus Cycles
Bus Cycle Master read cycle (channel R) Master read cycle (channel A) Master write cycle (channel B) Read cycle (RAM I/O) Write cycle (RAM I/O) Read cycle (I/O RAM) Write cycle (I/O RAM) Byte Word Byte Word Byte Word Byte Word DTARH DTAR H'FF SOS decoder H'FF SOS decoder Upper Address Bus DTARH DTARH DTARH DTARH Lower Address Bus DPDRRQ DTARA DTARB DTAR Upper Data Bus DPDRRQ DPDRR DPDRW DTDRH DTDRH DTDRH DTDRH, L DTDRH DTDRH, L DTDRH DTDRH Lower Data Bus -- -- -- -- DTDRL -- -- -- -- -- DTDRL
112
Data bus, upper 8 bits
[Module slave data bus]
DTDRH Data bus, lower 8 bits
Address Register Boundary: The number of bytes of on-chip RAM transferred by the DTU is determined by the DTAR settings and the boundary designated by DTCR bits BUD2 to BUD0. (See page 87) First, DTARH determines a 256-byte on-chip RAM area within which the DTU operates. BUD2 to BUD0 specify a 1-, 2-, 4-, 8-, 16-, 32-, 64-, or 128-byte boundary. These eight settings divide the 256-byte area into 256, 128, 64, 32, 16, 8, 4, or 2 smaller areas, respectively, with boundary addresses set on the boundaries between adjacent areas. The starting address of a transfer is given by the contents of DTARA, DTARB, or DTARC. The ending address is the next boundary address. The contents of DTARA, DTARB, or DTARC are incremented at each transfer. When the transfer is completed as far as the boundary address, a boundary overflow occurs. The DTARA, DTARB, or DTARC contents do not increment past the boundary. The upper bits remain unchanged. The lower bits are initialized to the value stored in RLAR. In normal mode, the DTE bit is cleared. Figure 5.10 shows an example with 64-byte boundaries, in which the starting address is in the exact center of a 64-byte area, so that a boundary overflow occurs when 32 bytes have been transferred. In repeat mode, if there are further transfer requests, the transfer is repeated on the same 32-byte area.
Boundory points Set by BUD2 Lowest block address (H'xx00) to BUD0 64 bytes Boundary address (H'xx3F) Start address (H'xx60) Boundary address (H'xx7F) 64 bytes Boundary address (H'xxBF) 64 bytes Boundary address (H'xxFF) 32 bytes 32 bytes DTARA value in repeat mode
Figure 5.10 Example of Memory Map with 64-Byte Boundary (DTARH = H'xx, DTARA = H'60)
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Ring Buffer Operation: In repeat mode, DTU channel B can operate as a ring buffer. In ring buffer operation, a number of bytes equal to the boundary designation can be treated as a ring-type FIFO buffer on RAM. Data positions in this buffer are indicated by three pointers. The main pointer is DTARB, which points to the address that will be accessed at the next transfer request. One auxiliary pointer is RLARB, which points to the top address of a data block being transferred in accordance with a transfer protocol. If the transfer fails, it can be repeated from the address indicated by RLARB. The other auxiliary pointer is CPARB, which points to the top of the data that has not yet been processed by the CPU. If DTARB catches up with CPARB and the two match, an overrun error interrupt can be generated to report this abnormality.
Unprocessed data
CPARB (Unprocessed data pointer) RLARB (Top address) DTARB (Receive pointer) Receive operation (writing to RAM)
Data block being received
Data block being transmitted
RLARB (Top address) DTARB (Transmit pointer) CPARB (Unprocessed data pointer) Transmit operation (reading from RAM)
Untransmitted data
Figure 5.11 Pointer Operation in Ring Buffer
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5.3.2
DTU and PBI Initialization
Care is required when setting up the DTU and PBI for DPRAM or handshake mode, because this causes changes in the operating states of input/output pins. An initialization procedure for this setup is given below and shown in figure 5.12. When some DTU channels are used for I/O transfer instead of PBI transfer, these channels should be initialized after the procedure below. Register contents are assumed to be initial values. 1. Write the upper byte of the address of the RAM area to be used by the DTU in DTARH. This register is also used for I/O transfers. It must be initialized before I/O transfer begins. 2. Set the EWRQ bit in PCCSR to 1, or clear it to 0. If this bit is set to 1, output from the WRQ pin is enabled when the DPME bit is set. 3-1. Set the HSCE bit in IOCR to 1, or clear it to 0. This bit selects handshake mode or DPRAM mode when the DPME bit is set. The treatment of the CS and RS2 to RS0 inputs differs between handshake mode and DPRAM mode. 3-2. Set the DPEA and DPEB bits in IOCR to 1 or 0. In DPRAM mode, these bits select direct word mode or bound buffer mode. They also limit access to DTARA, DTARB, DTCRA, and DTCRB. Some write accesses to registers that are shared with other operating modes are disabled by hardware if they would interfere with the operation of the other mode. 4. Set the DPME bit in SYSCR to 1. This sets the pins to slave mode (DPRAM mode or handshake mode) according to the chip operating mode (single-chip mode or expanded mode). Pins DDB7 to DDB0 (XDDB7 to XDDB0) are set for input/output, CS (XCS), RS 2 to RS0, WE (XWE), and OE (XOE) for input, and RDY (XRDY) and WRQ for output. Pins WRQ, CS, and RS2 to RS0 also depend on the settings of the EWRQ and HSCE bits. At the same time, it becomes possible to set and clear the QREF, MWEF, and MREF flags in PCCSR. The inputs at CS, WE, OE, etc. must be kept at the inactive level until initialization is completed. 5. Set the EWAKAR, ERAKAR, EMWI, and EMRI bits in PCCSR to 1, or clear them to 0. These bits select the usage of the RDY pin and enable or disable interrupts to the internal CPU. The usage of the RDY pin can be set from the master CPU. Data can now be transferred in DPRAM mode or handshake mode by accessing registers PCCSR, DTCRA, DTCRB, DTARA, DTARB, DPDRRH, DPDRRL, DPDRWH, and DPDRWL according to the operating mode.
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Initial setup
1
Set DTARH Initial setup for I/O transfer
2
Set PCCSR (EWRQ) Set IOCR (RPEA/B/C)
3
Set IOCR (HSCE, DPEA, DPEB) Set DTCRA/B/C (SOS2 to SOS0, BUD2 to BUD0)
4
Set SYSCR (DPME)
5
Set PCCSR (EMWI, EMRI) Set PCCSR (EWAKAR, ERAKAR) Buffer query operation in DPRAM mode DPRAM bound buffer mode
Carry out transfer, making necessary settings in on-chip RAM, DTARA/B/C, and DTCRA/B/C Carry out transfer, making necessary settings in on-chip RAM and PCCSR Carry out transfer, making necessary settings in on-chip RAM, DTARA/B, DTCRA/B, and PCCSR Carry out transfer, making necessary settings in DPDR registers and PCCSR
DPRAM direct word mode Handshake mode
Figure 5.12 DTU and PBI Initialization Flowchart 5.3.3 I/O Transfer Operations
The conditions under which I/O transfer is available are given below, with initialization and operating procedures.
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Conditions under Which I/O Transfer is Available * Channel R Permanently connected to the PBI. This channel is not available for I/O transfer. * Channel A Connected to the PBI when DPME = 1, HSCE = 0, and DPEA = 1. Available for I/O transfer at other times. * Channel B Connected to the PBI when DPME = 1, HSCE = 0, and DPEB = 1. Available for I/O transfer at other times. * Channel C Always available for I/O transfer. I/O Transfer Procedure (See figure 5.13.) 1. Write the upper byte of the address of the RAM area to be used by the DTU in DTARH. This register is also used for PBI transfers. It must be initialized before PBI transfer begins. 2. Set bits RPEA, RPEB, and RPEC in IOCR to 1 or clear them to 0 as necessary. 3. Set bits SOS2 to SOS0 and BUD2 to BUD0 in DTCRA, DTCRB, or DTCRC. 4. Initialize the on-chip supporting modules so that they will generate transfer requests for the desired I/O transfer. 5. For a transfer from RAM to an on-chip supporting module register, place the data to be transferred on RAM. Write the top address of the data on RAM in DTARA, DTARB, or DTARC. 6. Set the DTE bit to 1 in DTARA, DTARB, or DTARC. Set the DTIE bit to 1 in DTARA, DTARB, or DTARC as necessary. 7. Transfer requests are input from the on-chip supporting modules. The DTU responds by transferring data, then clearing the transfer request. DTARA, DTARB, or DTARC is incremented each time one byte is transferred. After repeated transfer requests, when the transfer reaches the boundary, in normal mode, a boundary overflow occurs and the DTE bit is cleared to 0. If the DTIE bit is set to 1, an interrupt is requested. 8. For a transfer from an on-chip supporting module to RAM, process the data transferred onto RAM. Steps 5 to 8 can be carried out repeatedly.
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Initial setup
1 2 3 4 5 6 7
Set DTARH
Set IOCR (RPEA/B/C) Set DTCRA/B/C (SOS2 to SOS0, BUD2 to BUD0) Initialize and activate on-chip supporting modules Set starting address in DTARA/B/C Set DTE and DTIE bits Wait for transfer request Input transfer request and get bus right Execute dead cycle No Executed by software Executed by hardware
Transfer request confirmed? Yes Execute read cycle
Present PBI transfer request? Not present Execute write cycle and release bus right Increment DTARA/B/C No
Insert PBI transfer cycle
Boundary reached? Yes What operating mode? Normal mode Clear DTE in DTCRA/B/C If DTIE is 1, generate boundary overflow interrupt
Repeat mode
Figure 5.13 I/O Transfer Flowchart
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I/O Transfer Precautions: When using I/O transfer, note the following points. * If software clears the DTE bit to 0, I/O operations will be suspended after the end of the bus cycle currently being executed. Although this is not a boundary overflow, if the condition DTE = 0 and DTIE = 1 is true, an interrupt request will be generated. To avoid generating an interrupt request, when clearing DTE, clear the DTIE bit to 0 at the same time. * While the DTE bit is set to 1, interrupt requests from the source selected by SOS2 to SOS0 will not be sent to the interrupt controller. Data should be prepared and processed after the DTE bit is cleared to 0, but if an interrupt request is generated before the DTE flag is set to 1 again, this interrupt request will go to the interrupt controller. To have interrupts handled by I/O transfer and not treated as CPU interrupt requests, the time taken to prepare and process data must be shorter than the time between interrupt requests. If this is not possible, software should implement a double-buffering scheme by writing to DTARA, DTARB, or DTARC at each boundary overflow to change the address. * After a transfer request is accepted from a supporting module, if the same transfer request occurs again before the old request is cleared (before the interrupt flag is cleared), the DTU will be unable to recognize the new request. The interval between transfer requests should be comfortably longer than the DTU's turnaround time. * If an I/O transfer is cancelled just when a transfer request occurs, the cancellation is carried out during the dead cycle. * The address relations of word access by the DTU need to be noted. In an I/O transfer, some supporting-module registers are accessed by word access, in which case the on-chip RAM is also accessed by word access. In word access, address bit 0 is disregarded, so the upper byte must be located at an even address and the lower byte at an odd address. The supportingmodule registers satisfy this condition, but it is possible to write odd addresses in the DTU address registers (DTARA, DTARB, DTARC) that specify the RAM address. When making a word-access I/O transfer, write an even address in the DTU address register. The transfer may not be performed as intended if an odd address is written. For example, if H'01 is written and word access is performed, the lower address bits will be output as H'00 in access to the upper byte, and H'01 in access to the lower byte.
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5.3.4
Buffer Query in DPRAM Mode
Buffer query in DPRAM mode provides a parallel interface with random access (read access) to a maximum 256 bytes of on-chip RAM. The interface makes use of DTU channel R to execute PBI transfers. Buffer query operations are depicted in block-diagram form in figure 5.14.
Master CPU (H8 microcontroller) CS RS2 to RS0 On-chip RAM CPU Data bus WE DTARH DPDRRQ QREF OE WRQ DDB7 to DDB0 Decoder A15 to A3 A2 to A0 WR RD WAIT D7 to D0
PBI: buffer query operation in DPRAM mode CPU address DTU address
Data bus
Figure 5.14 Buffer Query in DPRAM Mode The conditions under which buffer query is available are given below, with initialization and operating procedures. Conditions under Which Buffer Query is Available: Buffer query is available whenever the HSCE bit is cleared to 0 and the DPME bit is set to 1, enabling use of DPRAM-related pin functions. Availability is not affected by the mode of DTU channels A and B (DPRAM bound buffer mode or DPRAM direct word mode). Initialization and Operating Procedures (See figure 5.15.) 1. Initialize the DTU and PBI by the DTU/PBI initialization procedure. DTARH is also used in I/O transfers and DPRAM bound buffer mode. It must be initialized before these transfers begin. The EWRQ bit in PCCSR and the WRQ pin are also used in DPRAM bound buffer mode and DPRAM direct word mode. The initial settings must be free of conflict between modes. 2. When the master CPU writes to DPDRRQ, the QREF flag in PCCSR is set to 1 to indicate that DPDRRQ contains the lower 8 bits of an on-chip RAM address. 3. A transfer request is generated for DTU channel R, and the bus right is acquired for a master read cycle.
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4. The contents of the on-chip RAM address indicated by DTARH and DPDRRQ are transferred to DPDRRQ. The QREF flag is cleared to 0 to indicate that DPDRRQ contains a copy of onchip RAM data. 5. The master CPU should check that the QREF flag is 0, then read DPDRRQ. Precaution on Use of Buffer Query in DPRAM Mode: When using buffer query in DPRAM mode, note the following point: If the master CPU reads DPDRRQ while QREF = 1, the WRQ pin will stay at the low output level until QREF is cleared. If the master CPU does not use WRQ as a wait request signal, leave a sufficient interval from DPDRRQ write to DPDRRQ read to be sure that the transfer has been carried out.
Internal CPU
Trigger
Master CPU
Initial setup
1
Set DTARH
Executed by software
Set PCCSR (EWRQ)
Executed by hardware
Set SYSCR (DPME) and IOCR (HSCE)
Prepare data on on-chip RAM
Wait for transfer request WE
2
Write on-chip RAM address in DPDRRQ
3
Set QREF in PCCSR and get bus right 1 QREF 0
4
Transfer data from on-chip RAM to DPDRRQ Clear QREF in PCCSR and release bus right
5
Read DPDRRQ
Figure 5.15 Flowchart of Buffer Query in DPRAM Mode
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5.3.5
Operation in DPRAM Bound Buffer Mode
DPRAM bound buffer mode provides a parallel interface with sequential access to a maximum 128 bytes of on-chip RAM. The interface makes use of PBI transfers executed by DTU channels A and B. The conditions under which DPRAM bound buffer mode is available are given below, with initialization and operating procedures. Conditions under Which DPRAM Bound Buffer Mode is Available * DPRAM bound buffer mode, read access (DTU channel A) Available when DPME = 1, HSCE = 0, and DPEA = 1. * DPRAM bound buffer mode, write access (DTU channel B) Available when DPME = 1, HSCE = 0, and DPEB = 1. Initialization Procedure: Initialize the DTU and PBI by the DTU/PBI initialization procedure. DTARH is also used in I/O transfers, and in DPRAM buffer queries. It must be initialized before these transfers begin. The EWRQ bit in PCCSR and the WRQ and RDY pins are also used in DPRAM buffer queries and DPRAM direct word mode. The initial settings must be free of conflict between modes. (See tables 5.8 and 5.9.)
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Read Procedure for DPRAM Bound Buffer Mode: DPRAM bound buffer mode provides a parallel interface with sequential read access to a maximum 128 bytes of on-chip RAM, using PBI transfers executed by DTU channel A. Read operations in DPRAM bound buffer mode are depicted in block-diagram form in figure 5.16.
Master CPU (H8 microcontroller) CS DTCRA DTARH On-chip RAM DTARA RS2 to RS0 WE OE RDY WRQ DDB7 to DDB0 Decoder A15 to A3 A2 to A0 WR RD IRQ WAIT D7 to D0
PBI: DPRAM bound buffer mode, read access CPU address DTU address
DPDRRH MREF DPDRRL
CPU
Data bus
Data bus
Figure 5.16 Read Access in DPRAM Bound Buffer Mode
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The read procedure for DPRAM bound buffer mode is given below. (See figure 5.17.) 1. The internal CPU prepares the data to be transferred on on-chip RAM. The data should be located on contiguous addresses. Position the top address so that the last data will be located on a boundary address. The internal CPU sets the boundary in DTCRA and the top address in DTARA. 2. The internal CPU clears the MREF flag in PCCSR to notify the master CPU that preparations for the transfer are completed. If the ERAKAR bit is set to 1 in PCCSR, a low RDY signal is output. 3. The master CPU learns from the state of the RDY signal or MREF flag that transfer preparations have been completed, reads the boundary value in DTCRA and top address in DTARA, and calculates the number of bytes of data. The RDY output goes high. Then the master CPU reads the DPDRR registers a number of times equal to the number of data bytes. 4. When the master CPU reads DPDRR, the PBI requests a transfer on DTU channel A. The DTU gets the bus right and executes a master read cycle, transferring the contents of the onchip RAM address specified by DTARH and DTARA to an empty DPDRR register. Even and odd addresses in DTARA correspond to DPDRRH and DPDRRL, respectively. When the master CPU reads the DPDRR registers, it receives their data in the same order in which the data was transferred to the DPDRR registers. After being read, each DPDRR register becomes empty. Each time a DPDRR register becomes empty, the PBI requests another transfer on DTU channel A, to keep the DPDRR registers in the full state. 5. Each time it transfers one byte, the DTU increments DTARA. When the transfer reaches the boundary, a boundary overflow occurs and the MREF flag is set to 1. If the EMRI bit is set to 1, an interrupt is requested. Steps 1 to 5 can be carried out repeatedly.
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Internal CPU
Trigger
Master CPU
Initial setup Set DTARH Executed by software
Set PCCSR (EWRQ)
Executed by hardware
Set SYSCR (DPME) and IOCR (HSCE, DPEA)
Set PCCSR (EMRI)
MMREF 1
0
1
Prepare data on on-chip RAM
Set DTCRA (BUD2 to BUD0) and DTARA RDY OE 1
2
Clear MREF in PCCSR; RDY goes low
4
Get bus right and transfer data from on-chip RAM to DPDRR
MREF 0
5
Increment DTARA and release bus right
3
OE
Read DTCR (BUD2 to BUD0) and DTARA; RDY goes high
Yes
Boundary overflow? No
Read DPDRR
No
DPDRR register empty?
Yes
All bytes read? Yes
No
Set MREF in PCCSR
Process data
Figure 5.17 Flowchart of Read Operations in DPRAM Bound Buffer Mode
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Write Procedure for DPRAM Bound Buffer Mode: DPRAM bound buffer mode provides a parallel interface with sequential write access to a maximum 128 bytes of on-chip RAM, using PBI transfers executed by DTU channel B. Write operations in DPRAM bound buffer mode are depicted in block-diagram form in figure 5.18.
Master CPU (H8 microcontroller) CS DTCRB DTARH On-chip RAM DTARB RS2 to RS0 WE OE RDY WRQ DDB7 to DDB0 Decoder A15 to A3 A2 to A0 WR RD IRQ WAIT D7 to D0
PBI: DPRAM bound buffer mode, write access CPU address DTU address
DPDRWH MWEF DPDRWL
CPU
Data bus
Data bus
Figure 5.18 Write Access in DPRAM Bound Buffer Mode
126
The write procedure for DPRAM bound buffer mode is given below. (See figure 5.19.) 1. The internal CPU processes the data transferred to on-chip RAM, then clears the MWEF flag in PCCSR to notify the master CPU that it is ready for the next transfer. If the EWAKAR bit is set to 1 in PCCSR, a low RDY signal is output. 2. The master CPU learns from the state of the RDY signal or MWEF flag that transfer preparations have been completed, prepares data, and writes the top address in DTARB and the boundary of a destination area in on-chip RAM in DTCRB. The RDY output goes high. The master CPU writes all the data it has prepared to the DPDRW registers. 3. Each time the master CPU writes to the DPDRW registers, the data goes into a DPDRW register, which thereby becomes full. The PBI generates a transfer request for DTU channel B. The DTU transfers the data from the full DPDRW register to the on-chip RAM address specified by DTARH and DTARB. Even and odd addresses in DTARB correspond to DPDRWH and DPDRWL, respectively. Data is transferred in the order in which written. Each time data is written, the PBI requests a transfer on DTU channel B, to keep the DPDRW registers in the empty state. 4. Each time it transfers one byte, the DTU increments DTARB. When the transfer reaches the boundary, a boundary overflow occurs and the MWEF flag is set to 1. If the EMWI bit is set to 1, an interrupt is requested. Steps 1 to 4 can be carried out repeatedly.
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Internal CPU
Trigger
Master CPU
Initial setup Set DTARH Executed by software
Set PCCSR (EWRQ)
Executed by hardware
Set SYSCR (DPME) and IOCR (HSCE, DPEB) RDY
Set PCCSR (EWAKAR); RDY goes low
Set PCCSR (EMWI)
1
Clear MWEF in PCCSR; RDY goes low
RDY
1
MWEF 0
No
2
DPDRW register full? Yes
Process data
3
Get bus right and transfer data from DPDRW to on-chip RAM
Set DTCRB (BUD2 to BUD0) and DTARB; RDY goes high WE
Write to DPDRW
4
Increment DTARB and release bus right All bytes written? Yes No
Boundary overflow? Yes Set MWEF in PCCSR
No
Process data
Figure 5.19 Flowchart of Write Operations in DPRAM Bound Buffer Mode
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Precautions on Use of DPRAM Bound Buffer Mode: When using DPRAM bound buffer mode, note the following points: * If the master CPU reads a DPDRR register while it is empty, the WRQ pin will stay at the low output level until the register becomes full. If the master CPU does not use WRQ as a wait request signal, leave sufficient intervals between reads to be sure that the transfer is carried out. * If the master CPU writes to a DPDRW register while it is full, the WRQ pin will stay at the low output level until the register becomes empty. If the master CPU does not use WRQ as a wait request signal, leave sufficient intervals between writes to be sure that the transfer is carried out. * MWEF is initially 0, so when the EWAKAR bit is set to 1, the RDY output will go low immediately. Be careful of this at the start of the first transfer. * The RDY pin is shared by master read and master write in both DPRAM bound buffer mode and DPRAM direct word mode. If the master CPU uses RDY as an interrupt input, when it tries to learn the internal state of the DPRAM, there may be competing interrupt conditions. The master CPU should control the RDY output by using the ERAKAR and EWAKAR bits, or should check the MREF and MWEF flags at the start and end of transfer processing. 5.3.6 Operation in DPRAM Direct Word Mode
DPRAM direct word mode does not use the DTU. Read and write operations in DPRAM direct word mode are depicted in block-diagram form in figure 5.20.
Master CPU (H8 microcontroller) CS Data bus RS2 to RS0 WE CPU DPDRRH MREF DPDRRL DPDRWL DPDRWH MWEF RDY IRQ OE A2 to A0 WR RD Decoder A15 to A3
PBI: DPRAM direct word mode
DDB7 to DDB0
D7 to D0
Figure 5.20 Read/Write Access in DPRAM Direct Word Mode
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The conditions under which DPRAM direct word mode is available are given below, with initialization and operating procedures. Conditions under Which DPRAM Direct Word Mode is Available * DPRAM direct word mode, read access Available when DPME = 1, HSCE = 0, and DPEA = 0. * DPRAM direct word mode, write access Available when DPME = 1, HSCE = 0, and DPEB = 0. Initialization Procedure: Initialize the DTU and PBI by the DTU/PBI initialization procedure. The RDY pin is also used in DPRAM bound buffer mode. The initial settings must be free of conflict between modes. The initial state of the RDY pin is the high impedance state in single-chip mode, and the high output state in expanded modes. Read Procedure for DPRAM Direct Word Mode: For read access, DPRAM direct word mode provides a parallel interface with two data-register bytes that can be read by the master CPU and written to by the internal CPU. The read procedure for DPRAM direct word mode is given below. (See figure 5.21.) 1. The internal CPU writes data in DPDRRH and DPDRRL. Writing to DPDRRL clears the MREF flag in PCCSR. If the ERAKAR bit is set to 1 in PCCSR, a low RDY signal is output. 2. From the state of the RDY signal or MREF flag, the master CPU learns that the internal CPU has finished writing data. The master CPU now reads DPDRRH and DPDRRL. Reading DPDRRL sets the MREF flag to 1 in PCCSR. If the EMRI bit is set to 1, an interrupt is requested. The RDY output goes to the high impedance state in single-chip mode, and to the high output state in expanded modes.
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Internal CPU
Trigger
Master CPU
Initial setup Set PCCSR (EWRQ) Executed by software
Set SYSCR (DPME) and IOCR (HSCE, DPEA)
Executed by hardware
Set PCCSR (EMRI)
MREF 1
0
1
Write data in DPDRR registers At DPDRRL write, MREF is cleared and RDY goes low RDY
Set PCCSR (ERAKAR)
MREF 0 At DPDRRL read, MREF is set and RDY goes high OE
1
2
Read DPDRR
Process data
Figure 5.21 Flowchart of Read Operations in DPRAM Direct Word Mode
131
Write Procedure for DPRAM Direct Word Mode: For write access, DPRAM direct word mode provides a parallel interface with two data-register bytes that can be written to by the master CPU and read by the internal CPU. The write procedure for DPRAM direct word mode is given below. (See figure 5.22.) 1. From the state of the RDY signal or MWEF flag, the master CPU learns that the internal CPU has finished reading, and writes to DPDRWH and DPDRRL. Writing to DPDRWL sets the MWEF flag to 1 in PCCSR. If the EMWI bit is set to 1, an interrupt is requested. The RDY output goes to high impedance state in single-chip mode, and to high output state in expanded modes. 2. The internal CPU reads the data in DPDRWH and DPDRWL. Reading DPDRWL clears the MWEF flag in PCCSR. If the EWAKAR bit is set to 1 in PCCSR, a low RDY signal is output.
Internal CPU
Trigger
Master CPU
Initial setup Set PCCSR (EWRQ)
Set SYSCR (DPME) and IOCR (HSCE, DPEB)
Set PCCSR (EWAKAR)
Set PCCSR (EMWI)
2
At DPDRWL read, MWEF is cleared and RDY goes low
RDY
1
MWEF 0
Process data
Prepare data WE 1
At DPDRWL write, MWEF is set and RDY goes high
Write to DPDRW
Figure 5.22 Flowchart of Write Operations in DPRAM Direct Word Mode
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Precautions on Use of DPRAM Direct Word Mode: When using DPRAM direct word mode, note the following points: * MWEF is initially 0, so when the EWAKAR bit is set to 1, the RDY output will go low immediately. Be careful of this at the start of the first transfer. * The RDY pin is shared by master read and master write in both DPRAM bound buffer mode and DPRAM direct word mode. If the master CPU uses RDY as an interrupt input, when it tries to learn the internal state of the DPRAM, there may be competing interrupt conditions. The master CPU should control the RDY output by using the ERAKAR and EWAKAR bits, or should check the MREF and MWEF bits at the start and end of transfer processing. 5.3.7 Operation in Handshake Mode
Handshake mode provides a parallel interface in which data is passed through an 8-bit port one byte at a time. Figure 5.23 depicts handshake mode in block-diagram form. Figure 5.24 shows typical interconnections for handshaking communication.
Other chip Data bus WE OE CPU DPDRRL MREF DPDRWL MWEF RDY WRQ DDB7 to DDB0
PBI: handshake mode
Figure 5.23 Transfers in Handshake Mode
133
Transmit interface
WRQ MREF OE WE MWEF RDY DPDRRL DPDRWL DDB7 to DDB0
WE MWEF RDY WRQ MREF OE DPDRWL DBB7 to DBB0 DPDRRL
Transmit interface
Receive interface
Receive interface
(PBI)
(PBI)
Figure 5.24 Interconnections for Handshake Mode (Example) The conditions under which handshake mode is available are given below, with initialization, transmit, and receive procedures. Conditions under Which Handshake Mode is Available, and Initialization Procedure * Conditions under which handshake mode is available Available when DPME = 1 and HSCE = 1. * Initialization procedure Initialize the DTU and PBI by the DTU/PBI initialization procedure. Transmit Procedure in Handshake Mode: In transmitting in handshake mode, when the data register contents are output, a latch pulse is output from the WRQ pin to write the data into the handshake interface circuits in the receiving device. The transmit procedure for handshake mode is given below. (See figure 5.25.) 1. The internal CPU reads the MREF flag, checks that it is set to 1, and writes data in DPDRRL. The PBI then clears the MREF flag to 0 and outputs a low signal from the WRQ pin. 2. The PBI checks the state of the OE pin and outputs the DPDRRL contents if OE is low. After eight system clocks, the PBI automatically drives the WRQ output to the high level. 3. The PBI checks the state of the OE pin. When OE goes high, the PBI stops data output, places the data lines in the high-impedance state, and sets the MREF flag to 1.
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Transmitting interface (PBI)
Trigger
Receiving interface
Initial setup Set PCCSR (EWRQ) Executed by software
Set SYSCR (DPME) and IOCR (HSCE)
Executed by hardware
Set PCCSR (EMRI)
1
MREF 1 Write data in DPDRRL At DPDRRL write, MREF is cleared
0
WRQ OE Yes No
2
OE Low Output DPDRRL data
High
Ready to receive data?
No
Eight system clocks elapsed?
Yes
WRQ
Latch data
3
Set MREF
OE
Process data
Figure 5.25 Flowchart of Transmit Operations in Handshake Mode
135
Receive Procedure in Handshake Mode: In receiving in handshake mode, data input from the handshake interface in the transmitting device is read into the data register on a latch pulse input from the WE pin. (See figure 5.26.) 1. The PBI checks the states of the OE and WE pins. If a high-to-low transition of WE occurs while OE is high, a low signal is output from the RDY pin. 2. When WE goes high, the PBI latches the data into DPDRWL on the rising edge of WE and sets the MWEF bit to 1. 3. The internal CPU reads MWEF, checks that it is set to 1, and reads DPDRWL. The PBI then clears MWEF to 0 and drives the RDY output to the high level.
136
Receiving interface (PBI)
Trigger
Transmitting interface
Initial setup Set PCCSR (EWRQ) Executed by software
Set SYSCR (DPME) and IOCR (HSCE)
Executed by hardware
Set PCCSR (EMWI) WE High WE Low Low Preparations to transmit data completed
1
OE High
RDY WE
(Ready to receive data) Data transmission completed
Low
2
WE High Latch data into DPDRWL Set MWEF
3
Read MWEF, then read DPDRWL Clear MWEF
RDY
(Data reception completed)
Process data
Figure 5.26 Flowchart of Receive Operations in Handshake Mode
137
Precautions on Use of Handshake Mode: When using handshake mode, note the following points. * In handshake mode, it is possible to transmit and receive simultaneously, but care is required because the data bus is shared. Figures 5.27 and 5.28 (transmit) and 5.29 and 5.30 (receive) show typical interconnections for simultaneous transmitting and receiving with a device having an identical handshake mode. If both ends of the bidirectional WRQ line are brought from high to low at the same time, both OE pins will go high simultaneously and the data will collide. To avoid this, both devices should use a protocol in which they transmit and receive in turn, so that transmit requests will not occur simultaneously. * If the interface is used only for transmitting, the input at the WE pin should be held at the high level. For receive-only usage, the OE input should be held at the high level and the EWRQ bit should be cleared to 0 in PCCSR, since the WRQ output is not needed.
WE Transmitting interface (PBI) MREF DPDRRL WRQ OE DDB7 to DDB0
Held high for transmit-only
Receiving interface
Figure 5.27 Transmitting in Handshake Mode
WRQ 8 system clocks OE DBB7 to DBB0 DPDRRL write MREF
Figure 5.28 Transmit Timing in Handshake Mode
138
Receiving interface (PBI)
WE OE Held high for receive-only
Transmitting interface
MWEF DPDRWL
RDY DDB7 to DDB0
Figure 5.29 Receiving in Handshake Mode
WE RDY DBB7 to DBB0 DPDRWL read MWEF Does not go low until OE is high
Figure 5.30 Receive Timing in Handshake Mode
139
5.4
5.4.1
Application Notes
DTU and PBI Processing Time
PBI transfers due to buffer queries in DPRAM mode and some PBI transfers in DPRAM bound buffer mode are initiated by the rising edge of the WE or OE input signal when the PBI is accessed. The master CPU may receive a wait request from the WRQ pin if it accesses the PBI again after the edge is detected but before the PBI transfer is completed. The way to avoid this situation is to know how much time DTU and PBI processing takes, and allow sufficient intervals between PBI accesses. Examples are given below. In all these examples the master CPU is an H8 microcontroller. (1) When the master CPU accesses a PBI data register (DPDRRQ, DPDRRH/L, DPDRWH/L), the DTU is activated. The time until the same data register can be accessed again is the sum of the following three periods: * Transfer request detection lag: time lag from the detection of a rising edge at the WE or OE pin until the transfer request occurs * Bus cycle waiting time (maximum 6 states + wait states): time until the end of the bus cycle being executed when the transfer request occurs * DPRAM cycle (2 states + wait states): time for executing the bus cycle that transfers data between on-chip RAM and the PBI The transfer request detection lag depends on the operating mode. In DPRAM bound buffer mode, it is a maximum of 3.5 states, and in buffer query in DPRAM mode, it is a maximum of 3 states. If external memory is used instead of on-chip memory, and if the external memory is accessed with wait states, the maximum value of the bus cycle waiting time depends on the number of wait states. (2) In DPRAM bound buffer mode, the master CPU may access the PBI by byte access or word access. In word access, the minimum detectable interval (strobe interval) between the rising edges of OE and WE of two bytes is two states. (3) If input pins RS 2 to RS0 specify an unusable DPRAM data register and if pin CS is low, then pin WRQ also goes low. When pin WRQ is not used and the access interval is the time between the rising edge of OE and WE and the next confirmation of RS2 to RS0 and CS input, the following intervals become necessary. * Bound buffer mode access interval: 9.5 states (see figure 5.31) * Buffer query address write to data read access interval: 11 states (see figure 5.32) The above are consecutive accesses with the same channel. If different channels are used simultaneously, the PBI executes in order of the priority sequence of the channels. For accesses
140
with a low priority channel, the DPRAM cycle time executed first must be added to the access time. (4) Allowances for the times described in (1) to (3) above should be made with the master CPU operating frequency and AC characteristics taken into consideration. To make allowances for the strobe interval in a 3-state no-wait master CPU access, a master CPU with an operating frequency up to 1.5 times that of the interval CPU can be connected. In this case, the access intervals in (3) above become 14.25 states and 16.5 states of the master CPU. However, the output delay from the master CPU and the PBI input setup time for OE, WE, CS, and RS are different for each signal, and so adequate allowances must be made for these differences.
Transfer request detection time lag (max. 3.5 states) o RS0 to RS2 OE/WE Access interval (min. 9.5 states) Strobe interval (min. 2 states) Target data register not selected Bus cycle wait time (max. 3 x 2 states) DPRAM cycle (2 states) DPRAM cycle (2 states)
Figure 5.31 Bound Buffer Mode Access Interval
Transfer request detection time lag (max. 3 states) o RS0 to RS2 OE/WE Access interval (min. 11 states) Target data register not selected
CPU cycle wait time (max. 3 x 2 states)
DPRAM cycle (2 states)
Figure 5.32 Buffer Query Mode Address Write to Data Read Access Interval
141
Section 6 Wait-State Controller
6.1 Overview
The H8/3318 has an on-chip wait-state controller that enables insertion of wait states into bus cycles for interfacing to low-speed external devices. 6.1.1 Features
Features of the wait-state controller are listed below. * Three selectable wait modes: programmable wait mode, pin auto-wait mode, and pin wait mode * Automatic insertion of zero to three wait states 6.1.2 Block Diagram
Figure 6.1 shows a block diagram of the wait-state controller.
Internal data bus
WAIT
Wait-state controller (WSC) WSCR
Wait request signal
Legend WSCR: Wait-state control register
Figure 6.1 Block Diagram of Wait-State Controller
143
6.1.3
Input/Output Pins
Table 6.1 summarizes the wait-state controller's input pin. Table 6.1
Name Wait
Wait-State Controller Pins
Abbreviation WAIT I/O Input Function Wait request signal for access to external addresses
6.1.4
Register Configuration
Table 6.2 summarizes the wait-state controller's register. Table 6.2
Address H'FFC2
Register Configuration
Name Wait-state control register Abbreviation WSCR R/W R/W Initial Value H'08
6.2
6.2.1
Register Description
Wait-State Control Register (WSCR)
WSCR is an 8-bit readable/writable register that selects the wait mode for the wait-state controller (WSC) and specifies the number of wait states. It also controls frequency division of the clock signals supplied to the supporting modules.
Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 CKDBL 0 R/W 4 -- 1 -- 3 WMS1 1 R/W 2 WMS0 0 R/W 1 WC1 0 R/W 0 WC0 0 R/W
WSCR is initialized to H'C8 by a reset and in hardware standby mode. It is not initialized in software standby mode.
144
Bits 7 and 6--Reserved: These bits cannot be modified and are always read as 1. Bit 5--Clock Double (CKDBL): Controls frequency division of clock signals supplied to supporting modules. For details, see section 7, Clock Pulse Generator. Bit 4--Reserved: This bit is reserved, but it can be written and read. Its initial value is 0. Bits 3 and 2--Wait Mode Select 1 and 0 (WMS1/0): These bits select the wait mode.
Bit 3 WMS1 0 Bit 2 WMS0 0 1 1 0 1 Description Programmable wait mode No wait states inserted by wait-state controller Pin wait mode Pin auto-wait mode (Initial value)
Bits 1 and 0--Wait Count 1 and 0 (WC1/0): These bits select the number of wait states inserted automatically in access to external address areas.
Bit 1 WC1 0 Bit 0 WC0 0 1 1 0 1 Description No wait states inserted automatically by wait-state controller (Initial value) 1 state inserted 2 states inserted 3 states inserted
145
6.3
Wait Modes
Programmable Wait Mode: The number of wait states (TW ) selected by bits WC1 and WC0 are inserted in all accesses to external addresses. Figure 6.2 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1).
T1 T2 TW T3
o
Address bus
External address
AS
RD Read access Data bus Read data
WR Write access Data bus Write data
Figure 6.2 Programmable Wait Mode
146
Pin Wait Mode: In all accesses to external addresses, the number of wait states (TW) selected by bits WC1 and WC0 are inserted. If the WAIT pin is low at the fall of the system clock (o) in the last of these wait states, an additional wait state is inserted. If the WAIT pin remains low, wait states continue to be inserted until the WAIT signal goes high. Pin wait mode is useful for inserting four or more wait states, or for inserting different numbers of wait states for different external devices. Figure 6.3 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1) and one additional wait state is inserted by WAIT input.
Inserted by wait count T1 o T2 TW Inserted by WAIT signal TW T3
*
*
WAIT pin Address bus AS RD Read data Data bus WR Write access Data bus Note: * Arrows indicate time of sampling of the WAIT pin. Write data External address
Read access
Figure 6.3 Pin Wait Mode
147
Pin Auto-Wait Mode: If the WAIT pin is low, the number of wait states (TW) selected by bits WC1 and WC0 are inserted. In pin auto-wait mode, if the WAIT pin is low at the fall of the system clock (o) in the T2 state, the number of wait states (TW ) selected by bits WC1 and WC0 are inserted. No additional wait states are inserted even if the WAIT pin remains low. Pin auto-wait mode can be used for an easy interface to low-speed memory, simply by routing the chip select signal to the WAIT pin. Figure 6.4 shows the timing when the wait count is 1.
T1 T2 T3 T1 T2 TW T3
o
*
*
WAIT pin
Address bus
External address
External address
AS
RD Read access Data bus Read data Read data
WR Write access Data bus Write data Write data
Note: * Arrows indicate time of sampling of the WAIT pin.
Figure 6.4 Pin Auto-Wait Mode
148
Section 7 Clock Pulse Generator
7.1 Overview
The H8/3318 has a built-in clock pulse generator (CPG) consisting of an oscillator circuit, a duty adjustment circuit, and a divider and a prescaler that generates clock signals for the on-chip supporting modules. 7.1.1 Block Diagram
Figure 7.1 shows a block diagram of the clock pulse generator.
XTAL EXTAL
Oscillator circuit
Duty adjustment circuit
o (system clock)
oP (for supporting modules) Prescaler
Frequency divider (1/2) CKDBL oP/2 to oP/4096
Figure 7.1 Block Diagram of Clock Pulse Generator Input an external clock signal to the EXTAL pin, or connect a crystal resonator to the XTAL and EXTAL pins. The system clock frequency (o) will be the same as the input frequency. This same system clock frequency (oP) can be supplied to timers and other supporting modules, or it can be divided by two. The selection is made by software, by controlling the CKDBL bit. 7.1.2 Wait-State Control Register (WSCR)
WSCR is an 8-bit readable/writable register that controls frequency division of the clock signals supplied to the supporting modules. It also controls wait-state insertion. WSCR is initialized to H'C8 by a reset and in hardware standby mode. It is not initialized in software standby mode.
Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 CKDBL 0 R/W 4 -- 1 -- 3 WMS1 1 R/W 2 WMS0 0 R/W 1 WC1 0 R/W 0 WC0 0 R/W 149
Bits 7 and 6--Reserved: These bits cannot be modified and are always read as 1. Bit 5--Clock Double (CKDBL): Controls the frequency division of clock signals supplied to supporting modules.
Bit 5 CKDBL 0 1 Description The undivided system clock (o) is supplied as the clock (o P) for supporting modules (Initial value) The system clock (o) is divided by two and supplied as the clock (o P) for supporting modules
Bit 4--Reserved: This bit is reserved, but it can be written and read. Its initial value is 0. Bits 3 and 2--Wait Mode Select 1 and 0 (WMS1/0) Bits 1 and 0--Wait Count 1 and 0 (WC1/0) These bits control wait-state insertion. For details, see section 6, Wait-State Controller.
7.2
Oscillator Circuit
If an external crystal is connected across the EXTAL and XTAL pins, the on-chip oscillator circuit generates a system clock signal. Alternatively, an external clock signal can be applied to the EXTAL pin. 7.2.1 Connecting an External Crystal
Circuit Configuration: An external crystal can be connected as in the example in figure 7.2. Table 7.1 indicates the appropriate damping resistance Rd. An AT-cut parallel resonance crystal should be used.
C L1 EXTAL
XTAL
Rd
C L2
C L1 = C L2 = 10 pF to 22 pF
Figure 7.2 Connection of Crystal Oscillator (Example)
150
Table 7.1
Damping Resistance
2 1k 4 500 8 200 10 0 12 0 16 0
Frequency (MHz) Rd ()
Crystal Oscillator: Figure 7.3 shows an equivalent circuit of the crystal resonator. The crystal resonator should have the characteristics listed in table 7.2.
CL L XTAL Rs EXTAL
C0 AT-cut parallel resonating crystal
Figure 7.3 Equivalent Circuit of External Crystal Table 7.2 External Crystal Parameters
2 500 7 pF max 4 120 7 pF max 8 80 7 pF max 10 70 7 pF max 12 60 7 pF max 16 50 7 pF max
Frequency (MHz) Rd max () C0 (pF)
Use a crystal with the same frequency as the desired system clock frequency (o). Note on Board Design: When an external crystal is connected, other signal lines should be kept away from the crystal circuit to prevent induction from interfering with correct oscillation. See figure 7.4. The crystal and its load capacitors should be placed as close as possible to the XTAL and EXTAL pins.
151
Not allowed
Signal A
Signal B
C L2 XTAL
EXTAL C L1
Figure 7.4 Notes on Board Design around External Crystal 7.2.2 Input of External Clock Signal
Circuit Configuration: An external clock signal can be input as shown in the examples in figure 7.5. In example (b) in figure 7.5, the external clock signal should be kept high during standby. If the XTAL pin is left open, make sure the stray capacitance does not exceed 10 pF.
EXTAL
External clock input
XTAL
Open
(a) Connections with XTAL pin left open
EXTAL 74HC04 XTAL
External clock input
(b) Connections with inverted clock input at XTAL pin
Figure 7.5 External Clock Input (Example)
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External Clock Input: The external clock signal should have the same frequency as the desired system clock (o). Clock timing parameters are given in table 7.3 and figure 7.6. Table 7.3 Clock Timing
VCC = 2.7 to 5.5 V Item Symbol Min 40 Max -- VCC = 4.0 to 5.5 V Min 30 Max -- VCC = 5.0 V 10% Min 20 Max -- Unit Test Conditions ns Figure 7.6
t EXL Low pulse width of external clock input t EXH High pulse width of external clock input External clock rise time External clock fall time Clock pulse width low Clock pulse width high t EXr t EXf t CL
40
--
30
--
20
--
ns
-- -- 0.3 0.4
10 10 0.7 0.6 0.7 0.6
-- -- 0.3 0.4 0.3 0.4
10 10 0.7 0.6 0.7 0.6
-- -- 0.3 0.4 0.3 0.4
5 5 0.7 0.6 0.7 0.6
ns ns t cyc t cyc t cyc t cyc o 5 MHz Figure o < 5 MHz 19.4 o 5 MHz o < 5 MHz
t CH
0.3 0.4
tEXH
tEXL
EXTAL
VCC x 0.5
tEXr
tEXf
Figure 7.6 External Clock Input Timing Table 7.4 lists the external clock output stabilization delay time. Figure 7.7 shows the timing for the external clock output stabilization delay time. The oscillator and duty correction circuit have the function of regulating the waveform of the external clock input to the EXTAL pin. When the specified clock signal is input to the EXTAL pin, internal clock signal output is confirmed after the elapse of the external clock output stabilization delay time (t DEXT). As clock signal output is not confirmed during the tDEXT period, the reset signal should be driven low and the reset state maintained during this time.
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Table 7.4
External Clock Output Stabilization Delay Time
Conditions: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, VSS = AVSS = 0 V
Item External clock output stabilization delay time Symbol t DEXT* Min 500 Max -- Unit s Notes Figure 7.7
Note: * t DEXT includes a 10 tcyc RES pulse width (t RESW).
VCC
2.7 V
STBY EXTAL
VIH
o (internal and external) RES tDEXT* Note: * tDEXT includes a 10 tcyc RES pulse width (tRESW).
Figure 7.7 External Clock Output Stabilization Delay Time
7.3
Duty Adjustment Circuit
When the clock frequency is 5 MHz or above, the duty adjustment circuit adjusts the duty cycle of the signal from the oscillator circuit to generate the system clock (o).
7.4
Prescaler
The 1/2 frequency divider generates an on-chip supporting module clock (oP) from the system clock (o) according to the setting of the CKDBL bit. The prescaler divides the frequency of oP to generate internal clock signals with frequencies from o P/2 to oP/4096.
154
Section 8 I/O Ports
8.1 Overview
The H8/3318 has six 8-bit input/output ports, one 7-bit input/output port, one 3-bit input/output port, and one 8-bit input port. Table 8.1 lists the functions of each port in each operating mode. As table 8.1 indicates, the port functions are multiplexed with other functions, and the pin functions differ depending on the operating mode. Each port has a data direction register (DDR) that controls input and output, and a data register (DR) for storing output data. If bit manipulation instructions will be executed on the port data direction registers, see "Notes on Bit Manipulation Instructions" in section 2.5.5, Bit Manipulations. Ports 1, 2, 3, 4, 6, and 9 can drive one TTL load and a 90-pF capacitive load. Ports 5 and 8 can drive one TTL load and a 30-pF capacitive load. Ports 1 and 2 can drive LEDs (with 10-mA current sink). Ports 1 to 6, 8, and 9 can drive a darlington transistor. Ports 1 to 3 have built-in MOS pull-up transistors. For block diagrams of the ports, see appendix C, I/O Port Block Diagrams.
155
Table 8.1
Port Functions
Expanded Modes Single-Chip Mode Mode 3
Port
Description
Pins P17/A 7/TP7 to P10/A 0/TP0
Mode 1 A7 to A0
Mode 2
PBI Disabled (DPME = 0)
PBI Enabled (DPME = 1)
Port 1 * 8-bit I/O port * Input pullups * Can drive LEDs
P17/A 7 to Address output P10/A 0 (lower) General input when DDR = 0 (initial value)
P17/TP7 to P10/TP0 General input when DDR = 0 (initial value) General output when DDR = 1 and NDER = 0
Address output TPC output when DDR = 1 and (lower) when NDER = 1 DDR = 1 and NDER = 0 TPC output when DDR = 1 and NDER = 1
Port 2 * 8-bit I/O port * Input pullups * Can drive LEDs
P27/A 15 /TP15 to P20/A 8/TP8
P27/A 15 to Address output P20/A 8 (upper) General input when DDR = 0 and NDER = 0 (initial value)
A15 to A8
P27/TP15 to P20/TP8 General input when DDR = 0 (initial value) General output when DDR = 1 and NDER = 0
TPC output when DDR = 1 and Address output NDER = 1 (upper) when DDR = 1 and NDER = 1 TPC output when DDR = 1 and NDER = 1
Port 3 * 8-bit I/O port * Input pullups Port 4 * 8-bit I/O port
P37/D7/DDB7 to P30/D0/DDB0
D7 to D0 data bus
P37 to P30 General input/ output
DDB7 to DDB0 DPRAM data bus
P47/FTOB 1/XDDB7, P46/FTOA 1/XDDB6
P47/FTOB 1/XDDB7 to P40/TMCI0/XDDB0 General input/output or timer input/output (8-bit timer 0/1, input/output (8-bit timer 0/1, 16bit free-running timer 1) (TMCI 0, TMO0, TMRI0, TMCI1, TMO1, TMRI 1, FTOA1, FTOB1) when PBI is disabled (DPME = 0) DPRAM data bus when PBI is enabled (DPME = 1)
P47/FTOB 1, P46/FTOA 1 Free-running timer 1 output (FTOA1, FTOB1) or general input/output P45/TMRI1, P44/TMO1, P43/TMCI1, P42/TMRI0, P41/TMO0, P40/TMCI0 8-bit timer 0/1 input/output (TMCI0, TMO0, TMRI0, TMCI1, TMO1, TMRI1) and general input/output
P45/TMRI1/XDDB5, P44/TMO1/XDDB4, P43/TMCI1/XDDB3, P42/TMRI0/XDDB2, P41/TMO0/XDDB1, P40/TMCI0/XDDB0
156
Table 8.1
Port Functions (cont)
Expanded Modes Single-Chip Mode Mode 3
Port
Description
Pins P52/SCK 0, P51/RxD0, P50/TxD0 P67/IRQ7/ETMO1, P66/FTOB 0/IRQ6/ ETMRI1, P65/FTID/ETMCI1, P64/FTIC/ETMO0, P63/FTIB/ETMRI 0, P62/FTIA/FTI, P61/FTOA 0, P60/FTCI/ETMCI0
Mode 1
Mode 2
PBI Disabled (DPME = 0)
PBI Enabled (DPME = 1)
Port 5 * 3-bit I/O port Port 6 * 8-bit I/O port
General input/output or serial communication interface 0 input/output (TxD0, RxD0, SCK0) 16-bit free-running timer 0 input/output (FTCI, FTOA0, FTOB0, FTIA, FTIB, FTIC, FTID), 16-bit free-running timer 1 input (FTCI, FTI), interrupt input (IRQ6, IRQ7), and 8-bit general input/output when PBI is disabled (DPME = 0) The above and 8-bit timer 0/1 input/output (ETMCI 0, ETMRI0, ETMO0, ETMCI1, ETMRI1, ETMO1) when PBI is enabled (DPME = 1) Analog input to A/D converter (AN 7 to AN0) and general input Serial communication interface 1 input/output (TxD1, RxD1, SCK1), interrupt input (IRQ3, IRQ4, IRQ5), and general input/output 16-bit free-running timer 0 input/output (FTCI, FTOA0, FTOB0, FTIA, FTIB, FTIC, FTID), 16-bit free-running timer 1 input (FTCI, FTI), interrupt input (IRQ6, IRQ7), and 8-bit general input/output
Port 7 * 8-bit I/O port Port 8 * 7-bit I/O port
P77/AN7 to P70/AN0
P86/SCK 1/IRQ5/XOE, Serial communication interface 1 P85/RxD1/IRQ4, input/output (TxD1, RxD1, SCK1), P84/TxD1/IRQ3/XWE interrupt input (IRQ3, IRQ4, IRQ5), and general input/output when PBI is disabled (DPME = 0) XOE and XWE input, serial communication interface 1 input (RxD1), IRQ4 input, and general input/output when PBI is enabled (DPME = 1) P83/WRQ/XRDY
General input/output when PBI is General input/ disabled (DPME = 0) output WRQ and XRDY output when PBI is enabled (DPME = 1)
WRQ output
P82/RS2 to P8 0/RS0 General input/output when PBI is General input/ disabled (DPME = 0) RS2 to RS0 output input when PBI is enabled (DPME = 1)
RS2 to RS0 input
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Table 8.1
Port Functions (cont)
Expanded Modes Single-Chip Mode Mode 3
Port
Description
Pins
Mode 1 WAIT input
Mode 2
PBI Disabled (DPME = 0) General input/ output
PBI Enabled (DPME = 1) WE input
Port 9 * 8-bit I/O port P97/WAIT/WE P96/o
System clock (o) output
General input when DDR = 0 (initial value) System clock (o) output when DDR = 1
P95/AS/RDY P94/WR/OE P93/RD/CS P92/IRQ0, P91/IRQ1/XCS
AS output WR output RD output
General input/ output
RDY output OE input CS input
Interrupt input (IRQ0, IRQ1) or IRQ0 and IRQ1 input, and general input/output when PBI is general input/output disabled (DPME = 0) IRQ0 input, general input/output, and XCS input when PBI is enabled (DPME = 1)
P90/IRQ2/ADTRG
External trigger input to A/D converter (ADTRG), IRQ2 input, and general input/output
158
8.2
8.2.1
Port 1
Overview
Port 1 is an 8-bit input/output port that is multiplexed with the lower address output pins (A 7 to A0) and TPC output pins (TP7 to TP0). Figure 8.1 shows the pin configuration of port 1. The pin functions differ depending on the operating mode. Port 1 has built-in, software-controllable MOS input pull-up transistors that can be used in modes 2 and 3. Pins in port 1 can drive one TTL load and a 90-pF capacitive load. They can also drive LEDs and darlington transistors.
159
Port 1 pins P17/A7/TP7 P16/A6/TP6 P15/A5/TP5 Port 1 P14/A4/TP4 P13/A3/TP3 P12/A2/TP2 P11/A1/TP1 P10/A0/TP0
Pin configuration in mode 1 (expanded mode with on-chip ROM disabled) A7 (output) A6 (output) A5 (output) A4 (output) A3 (output) A2 (output) A1 (output) A0 (output)
Pin configuration in mode 2 (expanded mode with on-chip ROM enabled) A7 (output)/P17 (input)/TP7 (output) A6 (output)/P16 (input)/TP6 (output) A5 (output)/P15 (input)/TP5 (output) A4 (output)/P14 (input)/TP4 (output) A3 (output)/P13 (input)/TP3 (output) A2 (output)/P12 (input)/TP2 (output) A1 (output)/P11 (input)/TP1 (output) A0 (output)/P10 (input)/TP0 (output)
Pin configuration in mode 3 (single-chip mode) P17 (input/output)/TP7 (output) P16 (input/output)/TP6 (output) P15 (input/output)/TP5 (output) P14 (input/output)/TP4 (output) P13 (input/output)/TP3 (output) P12 (input/output)/TP2 (output) P11 (input/output)/TP1 (output) P10 (input/output)/TP0 (output)
Figure 8.1 Port 1 Pin Configuration
160
8.2.2
Register Configuration and Descriptions
Table 8.2 summarizes the port 1 registers. Table 8.2
Name Port 1 data direction register Port 1 data register Port 1 input pull-up control register
Port 1 Registers
Abbreviation P1DDR P1DR P1PCR Read/Write W R/W R/W Initial Value Address
H'FF (mode 1) H'FFB0 H'00 (modes 2 and 3) H'00 H'00 H'FFB2 H'FFAC
Port 1 Data Direction Register (P1DDR)
Bit 7 6 5 4 3 2 1 0
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Mode 1 Initial value Read/Write Modes 2 and 3 Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 1 --
P1DDR controls the input/output direction of each pin in port 1. * Mode 1 The P1DDR values are fixed at 1. Port 1 consists of lower address output pins. P1DDR values cannot be modified and are always read as 1. In hardware standby mode, the address bus is in the high-impedance state. * Mode 2 A pin in port 1 is used for address output or TPC output if the corresponding P1DDR bit is set to 1, and for general input if this bit is cleared to 0. * Mode 3 A pin in port 1 is used for general output or TPC output if the corresponding P1DDR bit is set to 1, and for general input if this bit is cleared to 0. In modes 2 and 3, P1DDR is a write-only register. Read data is invalid. If read, all bits always read 1. P1DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values, so if a transition to software standby mode occurs while a P1DDR bit is set to 1, the corresponding pin remains in the output state.
161
Port 1 Data Register (P1DR)
Bit 7 P17 Initial value Read/Write 0 R/W 6 P16 0 R/W 5 P15 0 R/W 4 P14 0 R/W 3 P13 0 R/W 2 P12 0 R/W 1 P11 0 R/W 0 P10 0 R/W
P1DR is an 8-bit register that stores data for pins P17 to P10. When a P1DDR bit is set to 1, if port 1 is read, the value in P1DR is obtained directly, regardless of the actual pin state. When a P1DDR bit is cleared to 0, if port 1 is read the pin state is obtained. P1DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. Port 1 Input Pull-Up Control Register (P1PCR)
Bit 7 P17PCR Initial value Read/Write 0 R/W 6 P16PCR 0 R/W 5 P15PCR 0 R/W 4 P14PCR 0 R/W 3 P13PCR 0 R/W 2 P12PCR 0 R/W 1 P11PCR 0 R/W 0 P10PCR 0 R/W
P1PCR is an 8-bit readable/writable register that controls the input pull-up transistors in port 1. If a P1DDR bit is cleared to 0 (designating input) and the corresponding P1PCR bit is set to 1, the input pull-up transistor is turned on. P1PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. 8.2.3 Pin Functions in Each Mode
Port 1 has different pin functions in different modes. A separate description for each mode is given below.
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Pin Functions in Mode 1: In mode 1 (expanded mode with on-chip ROM disabled), port 1 is automatically used for lower address output (A7 to A0). Figure 8.2 shows the pin functions in mode 1.
A7 (output) A6 (output) A5 (output) Port 1 A4 (output) A3 (output) A2 (output) A1 (output) A0 (output)
Figure 8.2 Pin Functions in Mode 1 (Port 1) Mode 2: In mode 2 (expanded mode with on-chip ROM enabled), port 1 can provide lower address output pins, TPC output pins, and general input pins. Each pin becomes a lower address output pin or TPC output pin if its P1DDR bit is set to 1, and a general input pin if its P1DDR bit is cleared to 0. Following a reset, all pins are input pins. To be used for address output or TPC output, their P1DDR bits must be set to 1. Figure 8.3 shows the pin functions in mode 2.
When P1DDR = 1 and NDER1 = 0 A7 (output) A6 (output) A5 (output) Port 1 A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) When P1DDR = 1 and NDER1 = 1 TP7 (output) TP6 (output) TP5 (output) TP4 (output) TP3 (output) TP2 (output) TP1 (output) TP0 (output)
When P1DDR = 0 P17 (input) P16 (input) P15 (input) P14 (input) P13 (input) P12 (input) P11 (input) P10 (input)
Figure 8.3 Pin Functions in Mode 2 (Port 1)
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Mode 3: In mode 3 (single-chip mode), port 1 can provide TPC output pins and general input/output pins. For general input/output, the input or output direction of each pin can be selected individually. A pin becomes a general input pin when its P1DDR bit is cleared to 0. When its P1DDR bit is set to 1, the pin becomes a general output pin if its NDER1 bit is cleared to 0, or a TPC output pin if its NDER1 bit is set to 1. Figure 8.4 shows the pin functions in mode 2.
When P1DDR = 0 (input), or P1DDR = 1 and NDER1 = 0 (output) P17 (input/output) P16 (input/output) P15 (input/output) Port 1 P14 (input/output) P13 (input/output) P12 (input/output) P11 (input/output) P10 (input/output)
When P1DDR = 1 and NDER1 = 1 TP7 (output) TP6 (output) TP5 (output) TP4 (output) TP3 (output) TP2 (output) TP1 (output) TP0 (output)
Figure 8.4 Pin Functions in Mode 3 (Port 1) 8.2.4 Input Pull-Up Transistors
Port 1 has built-in programmable input pull-up transistors that are available in modes 2 and 3. The pull-up for each bit can be turned on and off individually. To turn on an input pull-up in mode 2 or 3, set the corresponding P1PCR bit to 1 and clear the corresponding P1DDR bit to 0. P1PCR is cleared to H'00 by a reset and in the hardware standby mode, turning all input pull-ups off. In software standby mode, the previous state is maintained. Table 8.3 indicates the states of the input pull-up transistors in each operating mode. Table 8.3
Mode 1 2 3
States of Input Pull-Up Transistors (Port 1)
Reset Off Off Off Hardware Standby Off Off Off Software Standby Off On/off On/off Other Operating Modes Off On/off On/off
Notes: Off: The input pull-up transistor is always off. On/off: The input pull-up transistor is on if P1PCR = 1 and P1DDR = 0, but off otherwise.
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8.3
8.3.1
Port 2
Overview
Port 2 is an 8-bit input/output port that is multiplexed with the upper address output pins (A 15 to A8) and TPC output pins (TP15 to TP8). Figure 8.5 shows the pin configuration of port 2. The pin functions differ depending on the operating mode. Port 2 has built-in, software-controllable MOS input pull-up transistors that can be used in modes 2 and 3. Pins in port 2 can drive one TTL load and a 90-pF capacitive load. They can also drive LEDs and darlington transistors.
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Port 2 pins P27/A15/TP15 P26/A14/TP14 P25/A13/TP13 Port 2 P24/A12/TP12 P23/A11/TP11 P22/A10/TP10 P21/A9/TP9 P20/A8/TP8
Pin configuration in mode 1 (expanded mode with on-chip ROM disabled) A15 (output) A14 (output) A13 (output) A12 (output) A11 (output) A10 (output) A9 (output) A8 (output)
Pin configuration in mode 2 (expanded mode with on-chip ROM enabled) A15 (output)/P27 (input)/TP15 (output) A14 (output)/P26 (input)/TP14 (output) A13 (output)/P25 (input)/TP13 (output) A12 (output)/P24 (input)/TP12 (output) A11 (output)/P23 (input)/TP11 (output) A10 (output)/P22 (input)/TP10 (output) A9 (output)/P21 (input)/TP9 (output) A8 (output)/P20 (input)/TP8 (output)
Pin configuration in mode 3 (single-chip mode) P27 (input/output)/TP15 (output) P26 (input/output)/TP14 (output) P25 (input/output)/TP13 (output) P24 (input/output)/TP12 (output) P23 (input/output)/TP11 (output) P22 (input/output)/TP10 (output) P21 (input/output)/TP9 (output) P20 (input/output)/TP8 (output)
Figure 8.5 Port 2 Pin Configuration
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8.3.2
Register Configuration and Descriptions
Table 8.4 summarizes the port 2 registers. Table 8.4
Name Port 2 data direction register Port 2 data register Port 2 input pull-up control register
Port 2 Registers
Abbreviation P2DDR P2DR P2PCR Read/Write W R/W R/W Initial Value Address
H'FF (mode 1) H'FFB1 H'00 (modes 2 and 3) H'00 H'00 H'FFB3 H'FFAD
Port 2 Data Direction Register (P2DDR)
Bit 7 6 5 4 3 2 1 0
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Mode 1 Initial value Read/Write Modes 2 and 3 Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 1 --
P2DDR controls the input/output direction of each pin in port 2. * Mode 1 The P2DDR values are fixed at 1. Port 2 consists of upper address output pins. P2DDR values cannot be modified and are always read as 1. In hardware standby mode, the address bus is in the high-impedance state. * Mode 2 A pin in port 2 is used for address output or TPC output if the corresponding P2DDR bit is set to 1, and for general input if this bit is cleared to 0. * Mode 3 A pin in port 2 is used for general output or TPC output if the corresponding P2DDR bit is set to 1, and for general input if this bit is cleared to 0. In modes 2 and 3, P2DDR is a write-only register. Read data is invalid. If read, all bits always read 1. P2DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values, so if a transition to software standby mode occurs while a P2DDR bit is set to 1, the corresponding pin remains in the output state.
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Port 2 Data Register (P2DR)
Bit 7 P27 Initial value Read/Write 0 R/W 6 P26 0 R/W 5 P25 0 R/W 4 P24 0 R/W 3 P23 0 R/W 2 P22 0 R/W 1 P21 0 R/W 0 P20 0 R/W
P2DR is an 8-bit register that stores data for pins P27 to P20. When a P2DDR bit is set to 1, if port 2 is read, the value in P2DR is obtained directly, regardless of the actual pin state. When a P2DDR bit is cleared to 0, if port 2 is read the pin state is obtained. P2DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. Port 2 Input Pull-Up Control Register (P2PCR)
Bit 7 P27PCR Initial value Read/Write 0 R/W 6 P26PCR 0 R/W 5 P25PCR 0 R/W 4 P24PCR 0 R/W 3 P23PCR 0 R/W 2 P22PCR 0 R/W 1 P21PCR 0 R/W 0 P20PCR 0 R/W
P2PCR is an 8-bit readable/writable register that controls the input pull-up transistors in port 2. If a P2DDR bit is cleared to 0 (designating input) and the corresponding P2PCR bit is set to 1, the input pull-up transistor is turned on. P2PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. 8.3.3 Pin Functions in Each Mode
Port 2 has different pin functions in different modes. A separate description for each mode is given below.
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Pin Functions in Mode 1: In mode 1 (expanded mode with on-chip ROM disabled), port 2 is automatically used for upper address output (A15 to A8). Figure 8.6 shows the pin functions in mode 1.
A15 (output) A14 (output) A13 (output) Port 2 A12 (output) A11 (output) A10 (output) A9 (output) A8 (output)
Figure 8.6 Pin Functions in Mode 1 (Port 2) Mode 2: In mode 2 (expanded mode with on-chip ROM enabled), port 2 can provide upper address output pins, TPC output pins, and general input pins. Each pin becomes an upper address output pin or TPC output pin if its P2DDR bit is set to 1, and a general input pin if its P2DDR bit is cleared to 0. Following a reset, all pins are input pins. To be used for address output or TPC output, their P2DDR bits must be set to 1. Figure 8.7 shows the pin functions in mode 2.
When P2DDR = 1 and NDER2 = 0 A15 (output) A14 (output) A13 (output) Port 2 A12 (output) A11 (output) A10 (output) A9 (output) A8 (output) When P2DDR = 1 and NDER2 = 1 TP15 (output) TP14 (output) TP13 (output) TP12 (output) TP11 (output) TP10 (output) TP9 (output) TP8 (output)
When P2DDR = 0 P27 (input) P26 (input) P25 (input) P24 (input) P23 (input) P22 (input) P21 (input) P20 (input)
Figure 8.7 Pin Functions in Mode 2 (Port 2)
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Mode 3: In mode 3 (single-chip mode), port 2 can provide TPC output pins and general input/output pins. For general input/output, the input or output direction of each pin can be selected individually. A pin becomes a general input pin when its P2DDR bit is cleared to 0. When its P2DDR bit is set to 1, the pin becomes a general output pin if its NDER2 bit is cleared to 0, or a TPC output pin if its NDER2 bit is set to 1. Figure 8.8 shows the pin functions in mode 2.
When P2DDR = 0 (input), or P2DDR = 1 and NDER2 = 0 (output) P27 (input/output) P26 (input/output) P25 (input/output) Port 2 P24 (input/output) P23 (input/output) P22 (input/output) P21 (input/output) P20 (input/output)
When P2DDR = 1 and NDER2 = 1 TP15 (output) TP14 (output) TP13 (output) TP12 (output) TP11 (output) TP10 (output) TP9 (output) TP8 (output)
Figure 8.8 Pin Functions in Mode 3 (Port 2) 8.3.4 Input Pull-Up Transistors
Port 2 has built-in programmable input pull-up transistors that are available in modes 2 and 3. The pull-up for each bit can be turned on and off individually. To turn on an input pull-up in mode 2 or 3, set the corresponding P2PCR bit to 1 and clear the corresponding P2DDR bit to 0. P2PCR is cleared to H'00 by a reset and in the hardware standby mode, turning all input pull-ups off. In software standby mode, the previous state is maintained. Table 8.5 indicates the states of the input pull-up transistors in each operating mode. Table 8.5
Mode 1 2 3
States of Input Pull-Up Transistors (Port 2)
Reset Off Off Off Hardware Standby Off Off Off Software Standby Off On/off On/off Other Operating Modes Off On/off On/off
Notes: Off: The input pull-up transistor is always off. On/off: The input pull-up transistor is on if P2PCR = 1 and P2DDR = 0, but off otherwise.
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8.4
8.4.1
Port 3
Overview
Port 3 is an 8-bit input/output port that is multiplexed with the data bus (D7 to D0) and DPRAM data bus (DDB7 to DDB0). Figure 8.9 shows the pin configuration of port 3. The pin functions differ depending on the operating mode. Port 3 has built-in, software-controllable MOS input pull-up transistors that can be used in mode 3. Pins in port 3 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington transistor.
Pin configuration in mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded mode with on-chip ROM enabled) D7 (input/output) D6 (input/output) D5 (input/output) D4 (input/output) D3 (input/output) D2 (input/output) D1 (input/output) D0 (input/output) Pin configuration in mode 3 (single-chip mode) P37 (input/output)/DDB7 (input/output) P36 (input/output)/DDB6 (input/output) P35 (input/output)/DDB5 (input/output) P34 (input/output)/DDB4 (input/output) P33 (input/output)/DDB3 (input/output) P32 (input/output)/DDB2 (input/output) P31 (input/output)/DDB1 (input/output) P30 (input/output)/DDB0 (input/output)
Port 3 pins P37/D7/DDB7 P36/D6/DDB6 P35/D5/DDB5 Port 3 P34/D4/DDB4 P33/D3/DDB3 P32/D2/DDB2 P31/D1/DDB1 P30/D0/DDB0
Figure 8.9 Port 3 Pin Configuration
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8.4.2
Register Configuration and Descriptions
Table 8.6 summarizes the port 3 registers. Table 8.6
Name Port 3 data direction register Port 3 data register Port 3 input pull-up control register
Port 3 Registers
Abbreviation P3DDR P3DR P3PCR Read/Write W R/W R/W Initial Value H'00 H'00 H'00 Address H'FFB4 H'FFB6 H'FFAE
Port 3 Data Direction Register (P3DDR)--H'FFB4
Bit 7 6 5 4 3 2 1 0
P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
P3DDR is an 8-bit register that controls the input/output direction of each pin in port 3. P3DDR is a write-only register. Read data is invalid. If read, all bits always read 1. * Modes 1 and 2 In mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded mode with onchip ROM enabled), the input/output directions designated by P3DDR are ignored. Port 3 automatically consists of the input/output pins of the 8-bit data bus (D7 to D0). The data bus is in the high-impedance state during reset, and during hardware and software standby. * Mode 3 When the DPME bit is cleared to 0 in SYSCR, a pin in port 3 is used for general output if the corresponding P3DDR bit is set to 1, and for general input if this bit is cleared to 0. P3DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values, so if a transition to software standby mode occurs while a P3DDR bit is set to 1, the corresponding pin remains in the output state. When the DPME bit is set to 1 (slave mode), P3DDR is cleared to H'00 and port 3 consists of input/output pins for the DPRAM data bus (DDB7 to DDB0). In software standby mode, the DPRAM data bus is in the high-impedance state. A reset or entry to hardware standby mode clears the DPME bit to 0 and initializes P3DDR to H'00.
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Port 3 Data Register (P3DR)
Bit 7 P37 Initial value Read/Write 0 R/W 6 P36 0 R/W 5 P35 0 R/W 4 P34 0 R/W 3 P33 0 R/W 2 P32 0 R/W 1 P31 0 R/W 0 P30 0 R/W
P3DR is an 8-bit register that stores data for pins P37 to P30. When a P3DDR bit is set to 1, if port 3 is read, the value in P3DR is obtained directly, regardless of the actual pin state. When a P3DDR bit is cleared to 0, if port 3 is read the pin state is obtained. P3DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. Port 3 Input Pull-Up Control Register (P3PCR)
Bit 7 P37PCR Initial value Read/Write 0 R/W 6 P36PCR 0 R/W 5 P35PCR 0 R/W 4 P34PCR 0 R/W 3 P33PCR 0 R/W 2 P32PCR 0 R/W 1 P31PCR 0 R/W 0 P30PCR 0 R/W
PP3PCR is an 8-bit readable/writable register that controls the input pull-up transistors in port 3. If a P3DDR bit is cleared to 0 (designating input) and the corresponding P3PCR bit is set to 1, the input pull-up transistor is turned on. P3PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. 8.4.3 Pin Functions in Each Mode
Port 3 has different pin functions in different modes. A separate description for each mode is given below.
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Pin Functions in Modes 1 and 2: In mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded mode with on-chip ROM enabled), port 3 is automatically used for the input/output pins of the data bus (D7 to D0). Figure 8.10 shows the pin functions in modes 1 and 2.
Modes 1 and 2 D7 (input/output) D6 (input/output) D5 (input/output) Port 3 D4 (input/output) D3 (input/output) D2 (input/output) D1 (input/output) D0 (input/output)
Figure 8.10 Pin Functions in Modes 1 and 2 (Port 3) Mode 3: In mode 3 (single-chip mode), when the DPME bit is cleared to 0 in SYSCR, each pin can be designated for general input or output. A pin becomes an output pin when its P3DDR bit is set to 1, and an input pin when this bit is cleared to 0. When the DPME bit is set to 1 (slave mode), port 3 becomes the DPRAM data bus (DDB7 to DDB0). P3DR should be cleared to H'00. P3DDR is automatically cleared to H'00. Figure 8.11 shows the pin functions in mode 3.
When DPME = 0 P37 (input/output) P36 (input/output) P35 (input/output) Port 3 P34 (input/output) P33 (input/output) P32 (input/output) P31 (input/output) P30 (input/output) When DPME = 1 DDB7 (input/output) DDB6 (input/output) DDB5 (input/output) DDB4 (input/output) DDB3 (input/output) DDB2 (input/output) DDB1 (input/output) DDB0 (input/output)
Figure 8.11 Pin Functions in Mode 3 (Port 3)
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8.4.4
Input Pull-Up Transistors
Port 3 has built-in programmable input pull-up transistors that are available in mode 3. The pull-up for each bit can be turned on and off individually. To turn on an input pull-up in mode 3, clear bit DPME of SYSCR and bit P3DDR to 0, then write 1 to P3PCR. When DPME is set to 1 (slave mode), input pull-ups cannot be turned on. Input pull-ups are turned off after a reset and in hardware standby mode. Table 8.7 indicates the states of the input pull-up transistors in each operating mode. Table 8.7
Mode 1 2 3 DPME = 0 DPME 1 (slave mode)
States of Input Pull-Up Transistors (Port 3)
Reset Off Off Off Hardware Standby Off Off Off Other Operating Modes Off Off On/off Off
Notes: Off: The input pull-up transistor is always off. On/off: The input pull-up transistor is on if P3DDR = 0 and P3PCR = 1, but off otherwise.
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8.5
8.5.1
Port 4
Overview
Port 4 is an 8-bit input/output port that is multiplexed with the DPRAM data bus (XDDB7 to XDDB0), with input/output pins (TMRI0, TMRI1, TMCI0, TMCI1, TMO0, TMO1) of 8-bit timers 0 and 1, and with output pins (FTOA1, FTOB 1) of 16-bit free running timer 1 (FRT1). Figure 8.12 shows the pin configuration of port 4. The pin functions differ depending on the operating mode. Pins in port 4 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington transistor.
Pin configuration in mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded mode with on-chip ROM enabled) Port 4 pins P47/FTOB1/XDDB7 P46/FTOA1/XDDB6 P45/TMRI1/XDDB5 Port 4 P44/TMO1/XDDB4 P43/TMCI1/XDDB3 P42/TMRI0/XDDB2 P41/TMO0/XDDB1 P40/TMCI0/XDDB0 When DPME = 0 P47 (input/output)/FTOB1 (output) P46 (input/output)/FTOA1 (output) P45 (input/output)/TMRI1 (input) P44 (input/output)/TMO1 (output) P43 (input/output)/TMCI1 (input) P42 (input/output)/TMRI0 (input) P41 (input/output)/TMO0 (output) P40 (input/output)/TMCI0 (input) Pin configuration in mode 3 (single-chip mode) P47 (input/output)/FTOB1 (output) P46 (input/output)/FTOA1 (output) P45 (input/output)/TMRI1 (input) P44 (input/output)/TMO1 (output) P43 (input/output)/TMCI1 (input) P42 (input/output)/TMRI0 (input) P41 (input/output)/TMO0 (output) P40 (input/output)/TMCI0 (input) When DPME = 1 XDDB7 (input/output) XDDB6 (input/output) XDDB5 (input/output) XDDB4 (input/output) XDDB3 (input/output) XDDB2 (input/output) XDDB1 (input/output) XDDB0 (input/output)
Figure 8.12 Port 4 Pin Configuration
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8.5.2
Register Configuration and Descriptions
Table 8.8 summarizes the port 4 registers. Table 8.8
Name Port 4 data direction register Port 4 data register
Port 4 Registers
Abbreviation P4DDR P4DR Read/Write W R/W Initial Value H'00 H'00 Address H'FFB5 H'FFB7
Port 4 Data Direction Register (P4DDR)
Bit 7 6 5 4 3 2 1 0
P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
P4DDR is an 8-bit register that controls the input/output direction of each pin in port 4. A pin functions as an output pin if the corresponding P4DDR bit is set to 1, and as an input pin if this bit is cleared to 0. P4DDR is a write-only register. Read data is invalid. If read, all bits always read 1. P4DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values, so if a transition to software standby mode occurs while a P4DDR bit is set to 1, the corresponding pin remains in the output state. If a transition to software standby mode occurs while port 4 is being used by an on-chip supporting module (for example, for 8-bit timer output), the on-chip supporting module will be initialized, so the pin will revert to general-purpose input/output, controlled by P4DDR and P4DR.
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Port 4 Data Register (P4DR)
Bit 7 P47 Initial value Read/Write 0 R/W 6 P46 0 R/W 5 P45 0 R/W 4 P44 0 R/W 3 P43 0 R/W 2 P42 0 R/W 1 P41 0 R/W 0 P40 0 R/W
P4DR is an 8-bit register that stores data for pins P47 to P40. When a P4DDR bit is set to 1, if port 4 is read, the value in P4DR is obtained directly, regardless of the actual pin state. When a P4DDR bit is cleared to 0, if port 4 is read the pin state is obtained. This also applies to pins used by onchip supporting modules. P4DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. 8.5.3 Pin Functions in Each Mode
Port 4 has different pin functions in different modes. A separate description for each mode is given below. Pin Functions in Modes 1 and 2: In mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded mode with on-chip ROM enabled), port 4 is multiplexed with the DPRAM data bus, (XDDB 7 to XDDB0), with input/output pins (TMRI0, TMRI1, TMCI0, TMCI1, TMO0, TMO1) of 8-bit timers 0 and 1, and with output pins (FTOA1, FTOB 1) of 16-bit free running timer 1 (FRT1). Table 8.9 indicates the pin functions in modes 1 and 2.
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Table 8.9
Pin P47/FTOB1/ XDDB7
Pin Functions in Modes 1 and 2
Pin Functions and Selection Method Bit DPME in SYSCR, bit OEB in TCR of FRT1, and bit P47DDR select the pin function as follows DPME OEB P47DDR Pin function 0 P47 input 0 1 P47 output 0 1 X FTOB1 output 1 X X XDDB7 input/output
P46/FTOA1/ XDDB6
Bit DPME in SYSCR, bit OEA in TCR of FRT1, and bit P46DDR select the pin function as follows DPME OEA P46DDR Pin function 0 P46 input 0 1 P46 output 0 1 X FTOA1 output 1 X X XDDB6 input/output
P45/TMRI1/ XDDB5
Bit DPME in SYSCR and bit P45DDR select the pin function as follows DPME P45DDR Pin function 0 P45 input 0 1 P45 output 1 X XDDB5 input/output
TMRI1 input TMRI1 input is usable when bits CCLR1 and CCLR0 are both set to 1 in TCR of 8-bit timer 1 P44/TMO1/ XDDB4 Bit DPME in SYSCR, bits OS3 to OS0 in TCSR of 8-bit timer 1, and bit P44DDR select the pin function as follows DPME OS3 to OS0 P4DDR Pin function 0 P44 input All 0 1 P44 output 0 Not all 0 X TMO1 output 1 X X XDDB4 input/output
X: 0 and 1 settings both give the same pin function.
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Table 8.9
Pin P43/TMCI1/ XDDB3
Pin Functions in Modes 1 and 2 (cont)
Pin Functions and Selection Method Bit DPME in SYSCR and bit P43DDR select the pin function as follows DPME P43DDR Pin function 0 P43 input 0 1 P43 output TMCI1 output TMCI1 input is usable when bits CKS2 to CKS0 in TCR of 8-bit timer 1 select an external clock source 1 X XDDB3 input/output
P42/TMRI0/ XDDB2
Bit DPME in SYSCR, bits CCLR1 and CCLR0 in TCR of 8-bit timer 0, and bit P42DDR select the pin function as follows DPME P42DDR Pin function 0 P42 input 0 1 P42 output 1 X XDDB2 input/output
TMRI0 input TMRI0 input is usable when bits CCLR1 and CCLR0 are both set to 1 in TCR of 8-bit timer 0 P41/TMO0/ XDDB1 Bit DPME in SYSCR, bits OS3 to OS0 in TCSR of 8-bit timer 0, and bit P41DDR select the pin function as follows DPME OS3 to OS0 P41DDR Pin function 0 P41 input All 0 1 P41 output 0 Not all 0 X TMO0 output 1 X X XDDB1 input/output
P40/TMCI0/ XDDB0
Bit DPME in SYSCR and bit P40DDR select the pin function as follows DPME P40DDR Pin function 0 P40 input 0 1 P40 output 1 X XDDB0 input/output
TMCI0 output TMCI0 input is usable when bits CKS2 to CKS0 in TCR of 8-bit timer 0 select an external clock source X: 0 and 1 settings both give the same pin function.
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Pin Functions in Mode 3: In mode 3 (single-chip mode), port 4 is multiplexed with input/output pins (TMRI0, TMRI1, TMCI0, TMCI1, TMO0, TMO1) of 8-bit timers 0 and 1, and with output pins (FTOA1, FTOB1) of 16-bit free running timer 1 (FRT1). Table 8.10 indicates the pin functions in mode 3. Table 8.10 Pin Functions in Mode 3
Pin P47/FTOB1 Pin Functions and Selection Method Bit OEB in TCR of FRT1 and bit P4 7DDR select the pin function as follows OEB P47DDR Pin function 0 P47 input 0 1 P47 output 1 X FTOB1 output
P46/FTOA1
Bit OEA in TCR of FRT1 and bit P4 6DDR select the pin function as follows OEA P46DDR Pin function 0 P46 input 0 1 P46 output 1 X FTOA1 output
P45/TMRI1 P45DDR Pin function 0 P45 input 1 P45 output
TMRI1 input TMRI1 input is usable when bits CCLR1 and CCLR0 are both set to 1 in TCR of 8-bit timer 1 P44/TMO1 Bits OS3 to OS0 in TCSR of 8-bit timer 1 and bit P4 4DDR select the pin function as follows OS3 to OS0 P44DDR Pin function 0 P44 input All 0 1 P44 output Not all 0 X TMO1 output
X: 0 and 1 settings both give the same pin function.
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Table 8.10 Pin Functions in Mode 3 (cont)
Pin P43/TMCI1 P43DDR Pin function 0 P43 input 1 P43 output Pin Functions and Selection Method
TMCI1 input TMCI1 input is usable when bits CKS2 to CKS0 in TCR of 8-bit timer 1 select an external clock source P42/TMRI0 P42DDR Pin function 0 P42 input 1 P42 output
TMRI0 input TMRI0 input is usable when bits CCLR1 and CCLR0 are both set to 1 in TCR of 8-bit timer 0 P41/TMO0 Bits OS3 to OS0 in TCSR of 8-bit timer 0 and bit P4 1DDR select the pin function as follows OS3 to OS0 P41DDR Pin function 0 P41 input All 0 1 P41 output Not all 0 X TMO0 output
P40/TMCI0 P40DDR Pin function 0 P40 input 1 P40 output
TMCI0 input TMCI0 input is usable when bits CKS2 to CKS0 in TCR of 8-bit timer 0 select an external clock source X: 0 and 1 settings both give the same pin function.
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8.6
8.6.1
Port 5
Overview
Port 5 is a 3-bit input/output port that is multiplexed with input/output pins (TxD 0, RxD0, SCK0) of serial communication interface 0. The port 5 pin functions are the same in all operating modes. Figure 8.13 shows the pin configuration of port 5. Pins in port 5 can drive one TTL load and a 30-pF capacitive load. They can also drive a darlington transistor.
Port 5 pins P52 (input/output)/SCK0 (input/output) Port 5 P51 (input/output)/RxD0 (input) P50 (input/output)/TxD0 (output)
Figure 8.13 Port 5 Pin Configuration 8.6.2 Register Configuration and Descriptions
Table 8.11 summarizes the port 5 registers. Table 8.11 Port 5 Registers
Name Port 5 data direction register Port 5 data register Abbreviation P5DDR P5DR Read/Write W R/W Initial Value H'F8 H'F8 Address H'FFB8 H'FFBA
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Port 5 Data Direction Register (P5DDR)
Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 1 0
P52DDR P51DDR P50DDR 0 R/W 0 R/W 0 R/W
P5DDR is an 8-bit register that controls the input/output direction of each pin in port 5. A pin functions as an output pin if the corresponding P5DDR bit is set to 1, and as an input pin if this bit is cleared to 0. P5DDR is a write-only register. Read data is invalid. If read, all bits always read 1. P5DDR is initialized to H'F8 by a reset and in hardware standby mode. In software standby mode it retains its existing values, so if a transition to software standby mode occurs while a P5DDR bit is set to 1, the corresponding pin remains in the output state. If a transition to software standby mode occurs while port 5 is being used by the SCI, the SCI will be initialized, so the pin will revert to general-purpose input/output, controlled by P5DDR and P5DR. Port 5 Data Register (P5DR)
Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 P52 0 R/W 1 P51 0 R/W 0 P50 0 R/W
P5DR is an 8-bit register that stores data for pins P52 to P50. Bits 7 to 3 are reserved. They cannot be modified, and are always read as 1. When a P5DDR bit is set to 1, if port 5 is read, the value in P5DR is obtained directly, regardless of the actual pin state. When a P5DDR bit is cleared to 0, if port 5 is read the pin state is obtained. This also applies to pins used as SCI pins. P5DR is initialized to H'F8 by a reset and in hardware standby mode. In software standby mode it retains its existing values.
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8.6.3
Pin Functions in Each Mode
Port 5 has the same pin functions in each operating mode. All pins can also be used as SCI0 input/output pins. Table 8.12 indicates the pin functions of port 5. Table 8.12 Pin Functions of Port 5
Pin P52/SCK0 Pin Functions and Selection Method Bit C/A in SMR of SCI0, bits CKE0 and CKE1 in SCR of SCI0, and bit P52DDR select the pin function as follows CKE1 C/A CKE0 P52DDR Pin function 0 P52 input 0 1 P52 output 0 1 -- SCK 0 output 0 1 -- -- SCK 0 output 1 -- -- -- SCK 0 input
P51/RxD0
Bit RE in SCR of SCI0 and bit P51DDR select the pin function as follows RE P51DDR Pin function 0 P51 input 0 1 P51 output 1 -- RxD0 input
P50/TxD0
Bit TE in SCR of SCI0 and bit P50DDR select the pin function as follows TE P50DDR Pin function 0 P50 input 0 1 P50 output 1 -- TxD0 output
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8.7
8.7.1
Port 6
Overview
Port 6 is an 8-bit input/output port that is multiplexed with input/output pins (FTOA0, FTOB0, FTIA to FTID, FTCI) of 16-bit free-running timer 0 (FRT0), with input pins (FTCI, FTI) of 16-bit free running timer 1 (FRT1), with input/output pins (ETMCI0, ETMRI0. ETMO0, ETMCI1, ETMRI1, ETMO1) of 8-bit timers 0 and 1, and with IRQ6 and IRQ7 input pins. The pin functions of P62 and P61 are the same in all operating modes. The pin functions of P6 7 to P63 and P60 differ depending on the operating mode. Figure 8.14 shows the pin configuration of port 6. Pins in port 6 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington transistor.
Pin configuration in mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded mode with on-chip ROM enabled) P67 (input/output)/IRQ7 (input)/ETMO1 (output) P66 (input/output)/FTOB0 (output)/IRQ6 (input)/ETMRI1 (input) P65 (input/output)/FTID (input)/ETMCI1 (input) P64 (input/output)/FTIC (input)/ETMO0 (output) P63 (input/output)/FTIB (input)/ETMRI0 (input) P62 (input/output)/FTIA (input)/FTI (input) P61 (input/output)/FTOA0 (output) P60 (input/output)/FTCI (input)/ETMCI0 (input) Pin configuration in mode 3 (single-chip mode) P67 (input/output)/IRQ7 (input) P66 (input/output)/IRQ6 (input)/FTOB0 (output) P65 (input/output)/FTID (input) P64 (input/output)/FTIC (input) P63 (input/output)/FTIB (input) P62 (input/output)/FTIA (input)/FTI (input) P61 (input/output)/FTOA0 (output) P60 (input/output)/FTCI (input)
Port 6 pins P67/IRQ7/ETMO1 P66/FTOB0/IRQ6/ETMRI1 P65/FTID/ETMCI1 Port 6 P64/FTIC/ETMO0 P63/FTIB/ETMRI0 P62/FTIA/FTI P61/FTOA0 P60/FTCI/ETMCI0
Figure 8.14 Port 6 Pin Configuration
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8.7.2
Register Configuration and Descriptions
Table 8.13 summarizes the port 6 registers. Table 8.13 Port 6 Registers
Name Port 6 data direction register Port 6 data register Abbreviation P6DDR P6DR Read/Write W R/W Initial Value H'00 H'00 Address H'FFB9 H'FFBB
Port 6 Data Direction Register (P6DDR)--H'FFB9
Bit 7 6 5 4 3 2 1 0
P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
P6DDR is an 8-bit register that controls the input/output direction of each pin in port 6. A pin functions as an output pin if the corresponding P6DDR bit is set to 1, and as an input pin if this bit is cleared to 0. P6DDR is a write-only register. Read data is invalid. If read, all bits always read 1. P6DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values, so if a transition to software standby mode occurs while a P6DDR bit is set to 1, the corresponding pin remains in the output state. If a transition to software standby mode occurs while port 6 is being used by an on-chip supporting module (for example, for free-running timer output), the on-chip supporting module will be initialized, so the pin will revert to general-purpose input/output, controlled by P6DDR and P6DR.
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Port 6 Data Register (P6DR)--H'FFBB
Bit 7 P67 Initial value Read/Write 0 R/W 6 P66 0 R/W 5 P65 0 R/W 4 P64 0 R/W 3 P63 0 R/W 2 P62 0 R/W 1 P61 0 R/W 0 P60 0 R/W
P6DR is an 8-bit register that stores data for pins P67 to P60. When a P6DDR bit is set to 1, if port 6 is read, the value in P6DR is obtained directly, regardless of the actual pin state. When a P6DDR bit is cleared to 0, if port 6 is read the pin state is obtained. This also applies to pins used as onchip supporting module pins. P6DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. 8.7.3 Pin Functions in Each Mode
Port 6 has different pin functions in different modes. A separate description for each mode is given below. Pin Functions in Modes 1 and 2: In mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded mode with on-chip ROM enabled), port 6 is multiplexed with input/output pins (FTCI, FTOA0, FTOB 0, FTIA, FTIB, FTIC, FTID) of 16-bit free-running timer 0 (FRT0), with input pins (FTCI, FTI) of 16-bit free running timer 1 (FRT1), and with IRQ6 and IRQ7 input pins. When the PBI is enabled (when DPME is 1), port 6 is also multiplexed with input/output pins (ETMRI0, ETMRI1, ETMCI0, ETMCI1, ETMO0, ETMO1) of 8-bit timers 0 and 1. When the PBI is disabled (DPME is 0), the input/output pins of 8-bit timers 0 and 1 are multiplexed with port 4. Figure 8.15 and table 8.14 indicate the pin functions in modes 1 and 2.
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When DPME = 0 P67 (input/output)/IRQ7 (input) P66 (input/output)/FTOB0 (output)/IRQ6 (input) P65 (input/output)/FTID (input) Port 6 P64 (input/output)/FTIC (input) P63 (input/output)/FTIB (input) P62 (input/output)/FTIA (input)/FTI (input) P61 (input/output)/FTOA0 (output) P60 (input/output)/FTCI (input) When DPME = 1 P67 (input/output)/IRQ7 (input)/ETMO1 (output) P66 (input/output)/FTOB0 (output)/IRQ6 (input)/ETMRI1 (input) P65 (input/output)/FTID (input)/ETMCI1 (input) P64 (input/output)/FTIC (input)/ETMO0 (output) P63 (input/output)/FTIB (input)/ETMRI0 (input) P62 (input/output)/FTIA (input)/FTI (input) P61 (input/output)/FTOA0 (output) P60 (input/output)/FTCI (input)/ETMCI0 (input)
Figure 8.15 Pin Functions in Modes 1 and 2 (Port 6)
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Table 8.14 Pin Functions in Modes 1 and 2
Pin P67/IRQ7/ ETMO1 Pin Functions and Selection Method Bit DPME in SYSCR, bits OS3 to OS0 in the timer control/status register (TCSR) of 8-bit timer 1, and bit P67DDR select the pin function as follows When bit DPME is 0 P67DDR Pin function 0 P67 input 1 P67 output IRQ7 input When bit DPME is 1 OS3 to OS0 P67DDR Pin function 0 P67 input All 0 1 P67 output IRQ7 input IRQ7 input is usable when bit IERQ7E is set to 1 in IER P66/FTOB0/ IRQ6/ETMRI1 Bit DPME in SYSCR, bit OEB in the timer output compare control register (TCR) of FRT0, and bit P66DDR select the pin function as follows When bit DPME is 0 OEB P66DDR Pin function 0 P66 input 0 1 P66 output IRQ6 input When bit DPME is 1 OEB P66DDR Pin function 0 P66 input 0 1 P66 output 1 X FTOB0 output 1 X FTOB0 output Not all 0 X ETMO1 output
IRQ6 input and ETMRI1 input IRQ6 input is usable when bit IERQ6E is set to 1 in IER. ETMRI1 input is usable when bits CCLR1 and CCLR0 are both set to 1 in TCR of 8-bit timer 1 X: 0 and 1 settings both give the same pin function.
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Table 8.14 Pin Functions in Modes 1 and 2 (cont)
Pin P65/FTID/ ETMCI1 Pin Functions and Selection Method Bit DPME in SYSCR and bit P65DDR select the pin function as follows When bit DPME is 0 P65DDR Pin function 0 P65 input 1 P65 output FTID input When bit DPME is 1 P65DDR Pin function 0 P65 input 1 P65 output
FTID input and ETMCI1 input ETMCI1 input is usable when bits CKS2 to CKS0 in TCR of 8-bit timer 1 select an external clock source P64/FTIC/ ETMO0 Bit DPME in SYSCR, bits OS3 to OS0 in TCSR of 8-bit timer 0, and bit P64DDR select the pin function as follows When bit DPME is 0 P64DDR Pin function 0 P64 input 1 P64 output FTIC input When bit DPME is 1 OS3 to OS0 P64DDR Pin function 0 P64 input All 0 1 P64 output FTIC input Not all 0 X ETMO0 output
X: 0 and 1 settings both give the same pin function.
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Table 8.14 Pin Functions in Modes 1 and 2 (cont)
Pin P63/FTIB/ ETMRI0 Pin Functions and Selection Method Bit DPME in SYSCR and bit P63DDR select the pin function as follows When bit DPME is 0 P63DDR Pin function 0 P63 input FTIB input When bit DPME is 1 P63DDR Pin function 0 P63 input 1 P63 output 1 P63 output
FTIB input and ETMRI 0 input ETMRI0 input is usable when bits CCLR1 and CCLR0 are both set to 1 in TCR of 8-bit timer 0 P62/FTIA/FTI P62DDR Pin function 0 P62 input 1 P62 output
FTIA input and FTI input
P61/FTOA0
Bit OEA in TOCR of FRT0 and bit P6 1DDR select the pin function as follows OEA P61DDR Pin function 0 P61 input 0 1 P61 output 1 X FTOA0 output
X: 0 and 1 settings both give the same pin function.
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Table 8.14 Pin Functions in Modes 1 and 2 (cont)
Pin P60/FTCI/ ETMCI0 Pin Functions and Selection Method Bit DPME in SYSCR and bit P60DDR select the pin function as follows When bit DPME is 0 P60DDR Pin function 0 P60 input 1 P60 output FTCI input When bit DPME is 1 P60DDR Pin function 0 P60 input 1 P60 output
FTCI input and ETMCI0 input FTCI input is usable by either FRT0 or FRT1 when bits CKS2 to CKS0 in its TCR select an external clock source ETMCI0 input is usable when bits CKS2 to CKS0 in TCR of 8-bit timer 0 select an external clock source
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Pin Functions in Mode 3: In mode 3 (single-chip mode), port 6 is multiplexed with input/output pins (FTCI, FTOA0, FTOB0, FTIA, FTIB, FTIC, FTID) of FRT0, with input pins (FTCI, FTI) of FRT1, and with IRQ6 and IRQ7 input pins. Figure 8.16 and table 8.15 indicate the pin functions in mode 3.
P67 (input/output)/IRQ7 (input) P66 (input/output)/FTOB0 (output)/IRQ6 (input) P65 (input/output)/FTID (input) Port 6 P64 (input/output)/FTIC (input) P63 (input/output)/FTIB (input) P62 (input/output)/FTIA (input)/FTI (input) P61 (input/output)/FTOA0 (output) P60 (input/output)/FTCI (input)
Figure 8.16 Pin Functions in Mode 3 (Port 6) Table 8.15 Pin Functions in Mode 3
Pin P67/IRQ7 P67DDR Pin function 0 P67 input 1 P67 output IRQ7 input IRQ7 input is usable when bit IERQ7E is set to 1 in the IRQ enable register (IER) P66/FTOB0/ IRQ6 Bit OEB in the timer output compare control register (TOCR) of FRT0 and bit P66DDR select the pin function as follows OEB P66DDR Pin function 0 P66 input 0 1 P66 output IRQ6 input IRQ6 input is usable when bit IERQ6E is set to 1 in IER X: 0 and 1 settings both give the same pin function. 1 X FTOB0 output Pin Functions and Selection Method
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Table 8.15 Pin Functions in Mode 3 (cont)
Pin P65/FTID P65DDR Pin function 0 P65 input 1 P65 output FTID input Pin Functions and Selection Method
P64/FTIC P64DDR Pin function 0 P64 input 1 P64 output FTIC input
P63/FTIB P63DDR Pin function 0 P63 input FTIB input 1 P63 output
P62/FTIA/FTI P62DDR Pin function 0 P62 input 1 P62 output
FTIA input and FTI input
P61/FTOA0
Bit OEA in TOCR of FRT0 and bit P6 1DDR select the pin function as follows OEA P61DDR Pin function 0 P61 input 0 1 P61 output 1 X FTOA0 output
P60/FTCI P60DDR Pin function 0 P60 input 1 P60 output FTCI input FTCI input is usable by either FRT0 or FRT1 when bits CKS2 to CKS0 in its TCR select an external clock source X: 0 and 1 settings both give the same pin function.
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8.8
8.8.1
Port 7
Overview
Port 7 is an 8-bit input port that also provides the analog input pins for the A/D converter module. The pin functions are the same in expanded and single-chip modes. Port 7 is an 8-bit input port that also provides the analog input pins for the A/D converter module. The pin functions are the same in all modes. Figure 8.17 shows the pin configuration of port 7.
Port 7 pins P77 (input)/AN7 (input) P76 (input)/AN6 (input) P75 (input)/AN5 (input) Port 7 P74 (input)/AN4 (input) P73 (input)/AN3 (input) P72 (input)/AN2 (input) P71 (input)/AN1 (input) P70 (input)/AN0 (input)
Figure 8.17 Port 7 Pin Configuration
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8.8.2
Register Configuration and Descriptions
Table 8.16 summarizes the port 7 registers. Port 7 is an input port, so there is no data direction register. Table 8.16 Port 7 Register
Name Port 7 data register Abbreviation P7DR Read/Write R Initial Value Undetermined Address H'FFBE
Port 7 Data Register (P7DR)
Bit 7 P77 Initial value Read/Write * R 6 P76 * R 5 P75 * R 4 P74 * R 3 P73 * R 2 P72 * R 1 P71 * R 0 P70 * R
Note: * Depends on the levels of pins P7 7 to P7 0.
When P7DR is read, the pin states are always read.
197
8.9
8.9.1
Port 8
Overview
Port 8 is a 7-bit input/output port that is multiplexed with dual-port RAM (DPRAM) input/output pins (RS2 to RS0, XOE, XWE, WRQ, XRDY), with input/output pins (TxD1, RxD1, SCK1) of serial communication interface 1, and with interrupt input pins (IRQ5 to IRQ3). The functions of pins P85 and P82 to P80 are the same in all modes. The functions of pins P86, P84, and P83 differ depending on the operating mode. Figure 8.18 shows the pin configuration of port 8. Pins in port 8 can drive one TTL load and a 30-pF capacitive load. They can also drive a darlington transistor.
Pin configuration in mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded mode with on-chip ROM enabled) P86 (input/output)/SCK1 (input/output)/IRQ5 (input)/XOE (input) P85 (input/output)/RxD1 (input)/IRQ4 (input) P84 (input/output)/TxD1 (output)/IRQ3 (input)/XWE (input) P83 (input/output)/WRQ (output)/XRDY (output) P82 (input/output)/RS2 (input) P81 (input/output)/RS1 (input) P80 (input/output)/RS0 (input)
Port 8 pins P86/SCK1/IRQ5/XOE P85/RxD1/IRQ4 P84/TxD1/IRQ3/XWE Port 8 P83/WRQ/XRDY P82/RS2 P81/RS1 P80/RS0
Pin configuration in mode 3 (single-chip mode) P86 (input/output)/SCK1 (input/output)/IRQ5 (input) P85 (input/output)/RxD1 (input)/IRQ4 (input) P84 (input/output)/TxD1 (output)/IRQ3 (input) P83 (input/output)/WRQ (output) P82 (input/output)/RS2 (input) P81 (input/output)/RS1 (input) P80 (input/output)/RS0 (input)
Figure 8.18 Port 8 Pin Configuration
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8.9.2
Register Configuration and Descriptions
Table 8.17 summarizes the port 8 registers. Table 8.17 Port 8 Registers
Name Port 8 data direction register Port 8 data register Abbreviation P8DDR P8DR Read/Write W R/W Initial Value H'80 H'80 Address H'FFBD H'FFBF
Port 8 Data Direction Register (P8DDR)
Bit 7 -- Initial value Read/Write 1 -- 6 5 4 3 2 1 0
P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR 0 W 0 W 0 W 0 W 0 W 0 W 0 W
P8DDR is an 8-bit register that controls the input/output direction of each pin in port 8. A pin functions as an output pin if the corresponding P8DDR bit is set to 1, and as an input pin if this bit is cleared to 0. P8DDR is a write-only register. Read data is invalid. If read, all bits always read 1. Bit 7 is a reserved bit that always reads 1. P8DDR is initialized by a reset and in hardware standby mode. The initial value is H'80. In software standby mode P8DDR retains its existing values, so if a transition to software standby mode occurs while a P8DDR bit is set to 1, the corresponding pin remains in the output state. If a transition to software standby mode occurs while port 8 is being used by an on-chip supporting module (for example, for SCI input/output), the on-chip supporting module will be initialized, so the pin will revert to general-purpose input/output, controlled by P8DDR and P8DR. Port 8 Data Register (P8DR)
Bit 7 -- Initial value Read/Write 1 -- 6 P86 0 R/W 5 P85 0 R/W 4 P84 0 R/W 3 P83 0 R/W 2 P82 0 R/W 1 P81 0 R/W 0 P80 0 R/W
P8DR is an 8-bit register that stores data for pins P86 to P80. Bit 7 is a reserved bit that always reads 1.
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When a P8DDR bit is set to 1, if port 8 is read, the value in P8DR is obtained directly, regardless of the actual pin state. When a P8DDR bit is cleared to 0, if port 8 is read the pin state is obtained. This also applies to pins used by on-chip supporting modules. P8DR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode it retains its existing values. 8.9.3 Pin Functions in Each Mode
Port 8 has different pin functions in different modes. A separate description for each mode is given below. Pin Functions in Modes 1 and 2: In mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded mode with on-chip ROM enabled), port 8 is multiplexed with dual-port RAM (DPRAM) input/output pins (RS2 to RS0, XOE, XWE, WRQ, XRDY), with input/output pins (TxD 1, RxD1, SCK1) of serial communication interface 1 (SCI1), and with interrupt input pins (IRQ5 to IRQ3). Figure 8.19 and table 8.18 indicate the pin functions in modes 1 and 2.
When DPME = 0 P86 (input/output)/SCK1 (input/output)/IRQ5 (input) P85 (input/output)/RxD1 (input)/IRQ4 (input) P84 (input/output)/TxD1 (output)/IRQ3 (input) Port 8 P83 (input/output) P82 (input/output) P81 (input/output) P80 (input/output)
When DPME = 1 XOE (input) P85 (input/output)/RxD1 (input)/IRQ4 (input) XWE (input) WRQ (output)/XRDY (output) P82 (input/output)/RS2 (input) P81 (input/output)/RS1 (input) P80 (input/output)/RS0 (input)
Figure 8.19 Pin Functions in Modes 1 and 2 (Port 8)
200
Table 8.18 Pin Functions in Modes 1 and 2
Pin P86/SCK1/ IRQ5/XOE Pin Functions and Selection Method Bit DPME in SYSCR, bit C/A in SMR of SCI1, bits CKE0 and CKE1 in SCR of SCI1, and bit P8 6DDR select the pin function as follows DPME CKE1 C/A CKE0 P86DDR Pin function 0 P86 input 0 1 P86 output 0 1 X SCK 1 output 0 1 X X SCK 1 output IRQ5 input IRQ5 input is usable when bit IRQ5E is set to 1 in IER. P85/RxD1/ IRQ4 Bit RE in SCR of SCI1 and bit P85DDR select the pin function as follows RE P85DDR Pin function 0 P85 input 0 1 P85 output IRQ4 input IRQ4 input is usable when bit IRQ4E is set to 1 in IER. P84/TxD1/ IRQ3/XWE Bit DPME in SYSCR, bit TE in SCR of SCI1, and bit P8 4DDR select the pin function as follows DPME TE P84DDR Pin function 0 P84 input 0 1 P84 output 0 1 X TxD1 output 1 X X XWE input 1 X RxD1 input 0 1 X X X SCK 1 input 1 X X X X XOE input
IRQ3 input IRQ3 input is usable when bit IRQ3E is set to 1 in IER. X: 0 and 1 settings both give the same pin function.
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Table 8.18 Pin Functions in Modes 1 and 2 (cont)
Pin P83/WRQ/ XRDY Pin Functions and Selection Method Bit DPME in SYSCR, bit EWRQ in PCCSR of the PBI, and bit P83DDR select the pin function as follows DPME EWRQ P83DDR Pin function 0 P83 input 0 X 1 P83 output 0 X XRDY output 1 1 X WRQ output
P82/RS2
Bit DPME in SYSCR, bit HSCE in IOCR of the PBI, and bit P82DDR select the pin function as follows DPME HSCE P82DDR Pin function 0 P82 input 0 X 1 P82 output 0 P82 input 1 1 P82 output 1 0 X RS 2 input
P81/RS1
Bit DPME in SYSCR, bit HSCE in IOCR of the PBI, and bit P81DDR select the pin function as follows DPME HSCE P81DDR Pin function 0 P81 input 0 X 1 P81 output 0 P81 input 1 1 P81 output 1 0 X RS 1 input
P80/RS0
Bit DPME in SYSCR, bit HSCE in IOCR of the PBI, and bit P80DDR select the pin function as follows DPME HSCE P80DDR Pin function 0 P80 input 0 X 1 P80 output 0 P80 input 1 1 P80 output 1 0 X RS 0 input
X: 0 and 1 settings both give the same pin function.
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Pin Functions in Mode 3: In mode 3 (single-chip mode), port 8 is multiplexed with dual-port RAM (DPRAM) input/output pins (RS2 to RS0, WRQ), with input/output pins (TxD1, RxD1, SCK1) of serial communication interface 1 (SCI1), and with interrupt input pins (IRQ5 to IRQ3). Figure 8.20 and table 8.19 indicate the pin functions in mode 3.
When DPME = 0 P86 (input/output)/SCK1 (input/output)/IRQ5 (input) P85 (input/output)/RxD1 (input)/IRQ4 (input) P84 (input/output)/TxD1 (output)/IRQ3 (input) Port 8 P83 (input/output) P82 (input/output) P81 (input/output) P80 (input/output)
When DPME = 1 P86 (input/output)/SCK1 (input/output)/IRQ5 (input) P85 (input/output)/RxD1 (input)/IRQ4 (input) P84 (input/output)/TxD1 (output)/IRQ3 (input) P83 (input/output)/WRQ (output) P82 (input/output)/RS2 (input) P81 (input/output)/RS1 (input) P80 (input/output)/RS0 (input)
Figure 8.20 Pin Functions in Mode 3 (Port 8)
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Table 8.19 Pin Functions in Mode 3
Pin P86/SCK1/ IRQ5 Pin Functions and Selection Method Bit C/A in SMR of SCI1, bits CKE0 and CKE1 in SCR of SCI1, and bit P86DDR select the pin function as follows CKE1 C/A CKE0 P86DDR Pin function 0 P86 input 0 1 P86 output 0 1 X SCK 1 output IRQ5 input IRQ5 input is usable when bit IRQ5E is set to 1 in IER. P85/RxD1/ IRQ4 Bit RE in SCR of SCI1 and bit P85DDR select the pin function as follows RE P85DDR Pin function 0 P85 input 0 1 P85 output IRQ4 input IRQ4 input is usable when bit IRQ4E is set to 1 in IER. P84/TxD1/ IRQ3 Bit TE in SCR of SCI1 and bit P84DDR select the pin function as follows TE P84DDR Pin function 0 P84 input 0 1 P84 output IRQ3 input IRQ3 input is usable when bit IRQ3E is set to 1 in IER. X: 0 and 1 settings both give the same pin function. 1 X TxD1 output 1 X RxD1 input 0 1 X X SCK 1 output 1 X X X SCK 1 input
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Table 8.19 Pin Functions in Mode 3 (cont)
Pin P83/WRQ Pin Functions and Selection Method Bit DPME in SYSCR, bit EWRQ in PCCSR of the PBI, and bit P83DDR select the pin function as follows DPME EWRQ P83DDR Pin function 0 P83 input 0 X 1 P83 output 0 P83 input 0 1 P83 output 1 1 X WRQ output
P82/RS2
Bit DPME in SYSCR, bit HSCE in IOCR of the PBI, and bit P82DDR select the pin function as follows DPME HSCE P82DDR Pin function 0 P82 input 0 X 1 P82 output 0 P82 input 1 1 P82 output 1 0 X RS 2 input
P81/RS1
Bit DPME in SYSCR, bit HSCE in IOCR of the DTC, and bit P81DDR select the pin function as follows DPME HSCE P81DDR Pin function 0 P81 input 0 X 1 P81 output 0 P81 input 1 1 P81 output 1 0 X RS 1 input
P80/RS0
Bit DPME in SYSCR, bit HSCE in IOCR of the PBI, and bit P80DDR select the pin function as follows DPME HSCE P80DDR Pin function 0 P80 input 0 X 1 P80 output 0 P80 input 1 1 P80 output 1 0 X RS 0 input
X: 0 and 1 settings both give the same pin function.
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8.10
8.10.1
Port 9
Overview
Port 9 is an 8-bit input/output port that is multiplexed with interrupt input pins(IRQ0 to IRQ2), input/output pins for bus control signals (RD, WR, AS, WAIT), input/output pins (CS, OE, RDY, WE, XCS) for the dual-port RAM (DPRAM), an input pin (ADTRG) for the A/D converter, and an output pin (o) for the system clock. Pins P9 2 and P90 have the same functions in all modes. The functions of pins P97 to P93 and P91 differ depending on the operating mode. Figure 8.21 shows the pin configuration of port 9. Pins in port 9 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington pair.
Pin configuration in mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded mode with on-chip ROM enabled) WAIT (input) o (output) AS (output) WR (output) RD (output) P92 (input/output)/IRQ0 (input) P91 (input/output)/IRQ1 (input)/XCS (input) P90 (input/output)/IRQ2 (input)/ADTRG (input) Pin configuration in mode 3 (single-chip mode) P97 (input/output)/WE (input) P96 (input)/o (output) P95 (input/output)/RDY (output) P94 (input/output)/OE (input) P93 (input/output)/CS (input) P92 (input/output)/IRQ0 (input) P91 (input/output)/IRQ1 (input) P90 (input/output)/IRQ2 (input)/ADTRG (input)
Port 9 pins P97/WAIT/WE P96/o P95/AS/RDY Port 3 P94/WR/OE P93/RD/CS P92/IRQ0 P91/IRQ1/XCS P90/IRQ2/ADTRG
Figure 8.21 Port 9 Pin Configuration
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8.10.2
Register Configuration and Descriptions
Table 8.20 summarizes the port 9 registers. Table 8.20 Port 9 Registers
Name Port 9 data direction register Port 9 data register Abbreviation P9DDR P9DR Read/Write W R/W*1 Initial Value Address
H'40 (modes 1 and 2) H'FFC0 H'00 (mode 3) Undetermined* 2 H'FFC1
Notes: 1. Bit 6 is read-only. 2. Bit 6 is undetermined. Other bits are initially 0.
Port 9 Data Direction Register (P9DDR)
Bit 7 6 5 4 3 2 1 0
P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR Modes 1 and 2 Initial value Read/Write Mode 3 Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 1 -- 0 W 0 W 0 W 0 W 0 W 0 W
P9DDR is an 8-bit register that controls the input/output direction of each pin in port 9. A pin functions as an output pin if the corresponding P9DDR bit is set to 1, and as an input pin if this bit is cleared to 0. In modes 1 and 2, P96DDR is fixed at 1 and cannot be modified. P9DDR is a write-only register. Read data is invalid. If read, all bits always read 1. P9DDR is initialized by a reset and in hardware standby mode. The initial value is H'40 in modes 1 and 2, and H'00 in mode 3. In software standby mode P9DDR retains its existing values, so if a transition to software standby mode occurs while a P9DDR bit is set to 1, the corresponding pin remains in the output state.
207
Port 9 Data Register (P9DR)
Bit 7 P97 Initial value Read/Write 0 R/W 6 P96 * R 5 P95 0 R/W 4 P94 0 R/W 3 P93 0 R/W 2 P92 0 R/W 1 P91 0 R/W 0 P90 0 R/W
Note: * Determined by the level at pin P9 6.
P9DR is an 8-bit register that stores data for pins P97 to P90. When a P9DDR bit is set to 1, if port 9 is read, the value in P9DR is obtained directly, regardless of the actual pin state, except for P96. When a P9DDR bit is cleared to 0, if port 9 is read the pin state is obtained. This also applies to pins used by on-chip supporting modules and for bus control signals. P96 always returns the pin state. P9DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. 8.10.3 Pin Functions in Each Mode
Port 9 has one set of pin functions in modes 1 and 2, and a different set of pin functions in mode 3. The pins are multiplexed with IRQ0 to IRQ2 input, bus control signal input/output, DPRAM input/output, A/D converter input, and system clock (o) output. Table 8.21 indicates the pin functions of port 9.
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Table 8.21 Port 9 Pin Functions
Pin P97/WE/WAIT Pin Functions and Selection Method Bit DPME in SYSCR, bit P97DDR, and the operating mode select the pin function as follows Operating mode DPME P97DDR Pin function Modes 1 and 2 X X WAIT input 0 P97 input 0 1 P97 output Mode 3 1 X WE input
P96/o
Bit P96DDR and the operating mode select the pin function as follows Operating mode P96DDR Pin function Modes 1 and 2 Always 1 o output 0 P96 input Mode 3 1 o output
P95/RDY/AS
Bit DPME in SYSCR, bit P95DDR, and the operating mode select the pin function as follows Operating mode DPME P95DDR Pin function Modes 1 and 2 X X AS output 0 P95 input 0 1 P95 output Mode 3 1 X RDY output*
Note: * NMOS open-drain output. Connect an external pull-up resistor. P94/OE/WR Bit DPME in SYSCR, bit P94DDR, and the operating mode select the pin function as follows Operating mode DPME P94DDR Pin function Modes 1 and 2 X X WR output 0 P94 input 0 1 P94 output Mode 3 1 X OE input
X: 0 and 1 settings both give the same pin function.
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Table 8.21 Port 9 Pin Functions (cont)
Pin P93/CS/RD Pin Functions and Selection Method Bit DPME in SYSCR, bit HSCE in IOCR of the PBI, bit P9 3DDR, and the operating mode select the pin function as follows Operating mode DPME HSCE P93DDR Pin function Modes 1 and 2 X X X RD output 0 P93 input 0 X 1 P93 output 0 P93 input 1 1 P93 output Mode 3 1 0 X CS input
P92/IRQ0 P92DDR Pin function 0 P92 input IRQ0 input IRQ0 input can be used when bit IRQ0E is set to 1 in IER. P91/IRQ1/ XCS Bit DPME in SYSCR, bit P91DDR, and the operating mode select the pin function as follows Operating mode DPME P91DDR Pin function 0 P91 input 0 1 Modes 1 and 2 1 X 0 P91 input Mode 3 X 1 P91 output 1 P92 output
P91 output XCS input IRQ1 input
IRQ1 input
IRQ1 input can be used when bit IRQ1E is set to 1 in IER. P90/IRQ2/ ADTRG
P90DDR Pin function
0 P90 input
1 P90 output IRQ2 input and ADTRG input
IRQ2 input can be used when bit IRQ2E is set to 1 in IER. ADTRG input can be used when bit TRGE is set to 1 in ADCR. X: 0 and 1 settings both give the same pin function.
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8.11
8.11.1
Application Notes
Processing when Ports are Not Used
When a port is not used, designate it as an input port and pull each pin in the port either up or down individually. If a number of unused pins are pulled up or down with a single resistor, in the event of chip malfunction the pins will go to the output state, possibly resulting in collisions between outputs.
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Section 9 16-Bit Free-Running Timer 0
9.1 Overview
The H8/3318 has an on-chip 16-bit free-running timer (FRT) with two channels: FRT0 and FRT1. Each channel is based on a 16-bit free-running counter (FRC) and can generate two independent output waveforms, measure input pulse widths, or measure external clock periods. This section describes FRT0. For FRT1, see section 10, 16-Bit Free-Running Timer 1. The differences between FRT0 and FRT1 are that FRT0 has four input-capture lines and four input-capture interrupt sources, and allows buffering to be designated. FRT1 has only one inputcapture line and one input-capture interrupt source, and does not support buffering. 9.1.1 Features
The features of FRT0 are listed below. * Selection of four clock sources The free-running counter can be driven by an internal clock source (oP/2, oP/8, or oP/32), or an external clock input (enabling use as an external event counter). * Two independent comparators Each comparator can generate an independent waveform. * Four input capture channels The current count can be captured on the rising or falling edge (selectable) of an input signal. The four input capture registers can be used separately, or in a buffer mode. * Counter can be cleared under program control The free-running counters can be cleared on compare-match A. * Seven independent interrupts Compare-match A and B, input capture A to D, and overflow interrupts are requested independently.
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9.1.2
Block Diagram
Figure 9.1 shows a block diagram of free-running timer 0.
Internal clock sources oP/2 oP/8 oP/32 Clock Comparematch A OCRA (H/L)
External clock source FTCI Clock select
Comparator A
FTOA0 FTOB0
Overflow Clear Comparator B Bus interface FRC (H/L)
Internal data bus
Comparematch B
OCRB (H/L) Control logic FTIA FTIB FTIC FTID TCSR TIER TCR TOCR ICIA ICIB ICIC ICID OCIA OCIB FOVI Legend FRC: OCRA, B: ICRA, B, C, D: TCSR:
Capture
ICRA (H/L) ICRB (H/L) ICRC (H/L) ICRD (H/L)
Interrupt signals
Free-running counter (16 bits) Output compare register A, B (16 bits) Input capture register A, B, C, D (16 bits) Timer control/status register (8 bits)
TIER: Timer interrupt enable register (8 bits) TCR: Timer control register (8 bits) TOCR: Timer output compare control register (8 bits)
Figure 9.1 Block Diagram of 16-Bit Free-Running Timer 0
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Module data bus
9.1.3
Input and Output Pins
Table 9.1 lists the input and output pins of free-running timer 0. Table 9.1
Name Counter clock input Output compare A Output compare B Input capture A Input capture B Input capture C Input capture D
FRT0 Input and Output Pins
Abbreviation FTCI FTOA0* FTOB0* FTIA FTIB FTIC FTID I/O Input Output Output Input Input Input Input Function Input of external free-running counter clock signal Output controlled by comparator A Output controlled by comparator B Trigger for capturing current count into input capture register A Trigger for capturing current count into input capture register B Trigger for capturing current count into input capture register C Trigger for capturing current count into input capture register D
Note: * In this manual, the channel subscripts are normally omitted.
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9.1.4
Register Configuration
Table 9.2 lists the registers of free-running timer 0. Table 9.2
Name Timer interrupt enable register Timer control/status register Free-running counter (high) Free-running counter (low) Output compare register A/B (high)* Output compare register A/B (low)* 2 Timer control register Timer output compare control register Input capture register A (high) Input capture register A (low) Input capture register B (high) Input capture register B (low) Input capture register C (high) Input capture register C (low) Input capture register D (high) Input capture register D (low)
2
Register Configuration
Abbreviation TIER TCSR FRC (H) FRC (L) OCRA/B (H) OCRA/B (L) TCR TOCR ICRA (H) ICRA (L) ICRB (H) ICRB (L) ICRC (H) ICRC (L) ICRD (H) ICRD (L) R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R R R R R R R R
1
Initial Value H'01 H'00 H'00 H'00 H'FF H'FF H'00 H'E0 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00
Address H'FF90 H'FF91 H'FF92 H'FF93 H'FF94* 2 H'FF95* 2 H'FF96 H'FF97 H'FF98 H'FF99 H'FF9A H'FF9B H'FF9C H'FF9D H'FF9E H'FF9F
Notes: 1. Software can write a 0 to clear bits 7 to 1, but cannot write a 1 in these bits. 2. OCRA and OCRB share the same addresses. Access is controlled by the OCRS bit in TOCR.
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9.2
9.2.1
Bit
Register Descriptions
Free-Running Counter (FRC)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value Read/Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
FRC is a 16-bit readable/writable up-counter that increments on an internal pulse generated from a clock source. The clock source is selected by the clock select 1 and 0 bits (CKS1 and CKS0) of the timer control register (TCR). When FRC overflows from H'FFFF to H'0000, the overflow flag (OVF) in the timer control/status register (TCSR) is set to 1. Because FRC is a 16-bit register, a temporary register (TEMP) is used when FRC is written or read. See section 9.3, CPU Interface, for details. FRC is initialized to H'0000 by a reset and in the standby modes. It can also be cleared by compare-match A.
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9.2.2
Bit
Output Compare Registers A and B (OCRA and OCRB)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value Read/Write
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
OCRA and OCRB are 16-bit readable/writable registers, the contents of which are continually compared with the value in the FRC. When a match is detected, the corresponding output compare flag (OCFA or OCFB) is set in the timer control/status register (TCSR). In addition, if the output enable bit (OEA or OEB) in the timer output compare control register (TOCR) is set to 1, when the output compare register and FRC values match, the logic level selected by the output level bit (OLVLA or OLVLB) in TOCR is output at the output compare pin (FTOA or FTOB). Following a reset, the FTOA and FTOB output levels are 0 until the first compare-match. Because OCRA and OCRB are 16-bit registers, a temporary register (TEMP) is used for write access, as explained in section 9.3, CPU Interface. OCRA and OCRB are initialized to H'FFFF by a reset and in the standby modes. 9.2.3
Bit
Input Capture Registers A to D (ICRA to ICRD)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value Read/Write
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Each input capture register is a 16-bit read-only register. When the rising or falling edge of the signal at an input capture pin (FTIA to FTID) is detected, the current FRC value is copied to the corresponding input capture register (ICRA to ICRD).* At the same time, the corresponding input capture flag (ICFA to ICFD) in the timer control/status register (TCSR) is set to 1. The input capture edge is selected by the input edge select bits (IEDGA to IEDGD) in the timer control register (TCR). Note: * The FRC contents are transferred to the input capture register regardless of the value of the input capture flag (ICFA/B/C/D).
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Input capture can be buffered by using the input capture registers in pairs. When the BUFEA bit in TCR is set to 1, ICRC is used as a buffer register for ICRA as shown in figure 9.2. When an FTIA input is received, the old ICRA contents are moved into ICRC, and the new FRC count is copied into ICRA.
BUFEA IEDGA IEDGC
FTIA
Edge detect and capture signal generating circuit
ICRC BUFEA: IEDGA: IEDGC: ICRC: ICRA: FRC: Buffer enable A Input edge select A Input edge select C Input capture register C Input capture register A Free-running counter
ICRA
FRC
Figure 9.2 Input Capture Buffering (Example) Similarly, when the BUFEB bit in TCR is set to 1, ICRD is used as a buffer register for ICRB. When input capture is buffered, if the two input edge bits are set to different values (IEDGA IEDGC or IEDGB IEDGD), then input capture is triggered on both the rising and falling edges of the FTIA or FTIB input signal. If the two input edge bits are set to the same value (IEDGA = IEDGC or IEDGB = IEDGD), then input capture is triggered on only one edge. See table 9.3. Table 9.3
IEDGA 0
Buffered Input Capture Edge Selection (Example)
IEDGC 0 1 Input Capture Edge Captured on falling edge of input capture A (FTIA) (Initial value)
Captured on both rising and falling edges of input capture A (FTIA)
1
0 1 Captured on rising edge of input capture A (FTIA)
Because the input capture registers are 16-bit registers, a temporary register (TEMP) is used when they are read. See section 9.3, CPU Interface, for details.
219
To ensure input capture, the width of the input capture pulse should be at least 1.5 system clock periods (1.5*o). When triggering is enabled on both edges, the input capture pulse width should be at least 2.5 system clock periods. The input capture registers are initialized to H'0000 by a reset and in the standby modes. 9.2.4
Bit
Timer Interrupt Enable Register (TIER)
7 ICIAE 6 ICIBE 0 R/W 5 ICICE 0 R/W 4 ICIDE 0 R/W 3 OCIAE 0 R/W 2 OCIBE 0 R/W 1 OVIE 0 R/W 0 -- 1 --
Initial value Read/Write
0 R/W
TIER is an 8-bit readable/writable register that enables and disables interrupts. TIER is initialized to H'01 by a reset and in the standby modes. Bit 7--Input Capture Interrupt A Enable (ICIAE): This bit selects whether to request input capture interrupt A (ICIA) when input capture flag A (ICFA) in the timer status/control register (TCSR) is set to 1.
Bit 7 ICIAE 0 1 Description Input capture interrupt request A (ICIA) is disabled Input capture interrupt request A (ICIA) is enabled (Initial value)
Bit 6--Input Capture Interrupt B Enable (ICIBE): This bit selects whether to request input capture interrupt B (ICIB) when input capture flag B (ICFB) in TCSR is set to 1.
Bit 6 ICIBE 0 1 Description Input capture interrupt request B (ICIB) is disabled Input capture interrupt request B (ICIB) is enabled (Initial value)
Bit 5--Input Capture Interrupt C Enable (ICICE): This bit selects whether to request input capture interrupt C (ICIC) when input capture flag C (ICFC) in TCSR is set to 1.
Bit 5 ICICE 0 1 Description Input capture interrupt request C (ICIC) is disabled Input capture interrupt request C (ICIC) is enabled (Initial value)
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Bit 4--Input Capture Interrupt D Enable (ICIDE): This bit selects whether to request input capture interrupt D (ICID) when input capture flag D (ICFD) in TCSR is set to 1.
Bit 4 ICIDE 0 1 Description Input capture interrupt request D (ICID) is disabled Input capture interrupt request D (ICID) is enabled (Initial value)
Bit 3--Output Compare Interrupt A Enable (OCIAE): This bit selects whether to request output compare interrupt A (OCIA) when output compare flag A (OCFA) in TCSR is set to 1.
Bit 3 OCIAE 0 1 Description Output compare interrupt request A (OCIA) is disabled Output compare interrupt request A (OCIA) is enabled (Initial value)
Bit 2--Output Compare Interrupt B Enable (OCIBE): This bit selects whether to request output compare interrupt B (OCIB) when output compare flag B (OCFB) in TCSR is set to 1.
Bit 2 OCIBE 0 1 Description Output compare interrupt request B (OCIB) is disabled Output compare interrupt request B (OCIB) is enabled (Initial value)
Bit 1--Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a freerunning timer overflow interrupt (FOVI) when the timer overflow flag (OVF) in TCSR is set to 1.
Bit 1 OVIE 0 1 Description Timer overflow interrupt request (FOVI) is disabled Timer overflow interrupt request (FOVI) is enabled (Initial value)
Bit 0--Reserved: This bit cannot be modified and is always read as 1.
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9.2.5
Bit
Timer Control/Status Register (TCSR)
7 ICFA 6 ICFB 0 R/(W)* 5 ICFC 0 R/(W)* 4 ICFD 0 R/(W)* 3 OCFA 0 R/(W)* 2 OCFB 0 R/(W)* 1 OVF 0 R/(W)* 0 CCLRA 0 R/W
Initial value Read/Write
0 R/(W)*
Note: * Software can write 0 in bits 7 to 1 to clear the flags, but cannot write 1 in these bits.
TCSR is an 8-bit register that controls interrupt request signals and selects whether to clear the counter. TCSR is initialized to H'00 by a reset and in the standby modes. Timing is described in section 9.4, Operation. Bit 7--Input Capture Flag A (ICFA): This status bit is set to 1 to flag an input capture A event. If BUFEA = 0, ICFA indicates that the FRC value has been copied to ICRA. If BUFEA = 1, ICFA indicates that the old ICRA value has been moved into ICRC and the new FRC value has been copied to ICRA. ICFA must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 7 ICFA 0 1 Description To clear ICFA, the CPU must read ICFA after it has been set to 1, then write a 0 in this bit (Initial value) This bit is set to 1 when an FTIA input signal causes the FRC value to be copied to ICRA
Bit 6--Input Capture Flag B (ICFB): This status bit is set to 1 to flag an input capture B event. If BUFEB = 0, ICFB indicates that the FRC value has been copied to ICRB. If BUFEB = 1, ICFB indicates that the old ICRB value has been moved into ICRD and the new FRC value has been copied to ICRB. ICFB must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 6 ICFB 0 1 Description To clear ICFB, the CPU must read ICFB after it has been set to 1, then write a 0 in this bit (Initial value) This bit is set to 1 when an FTIB input signal causes the FRC value to be copied to ICRB
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Bit 5--Input Capture Flag C (ICFC): This status bit is set to 1 to flag input of a rising or falling edge of FTIC as selected by the IEDGC bit. When BUFEA = 0, this indicates capture of the FRC count in ICRC. When BUFEA = 1, however, the FRC count is not captured, so ICFC becomes simply an external interrupt flag. In other words, the buffer mode frees FTIC for use as a generalpurpose interrupt signal (which can be enabled or disabled by the ICICE bit). ICFC must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 5 ICFC 0 1 Description To clear ICFC, the CPU must read ICFC after it has been set to 1, then write a 0 in this bit (Initial value) This bit is set to 1 when an FTIC input signal is received
Bit 4--Input Capture Flag D (ICFD): This status bit is set to 1 to flag input of a rising or falling edge of FTID as selected by the IEDGD bit. When BUFEB = 0, this indicates capture of the FRC count in ICRD. When BUFEB = 1, however, the FRC count is not captured, so ICFD becomes simply an external interrupt flag. In other words, the buffer mode frees FTID for use as a generalpurpose interrupt signal (which can be enabled or disabled by the ICIDE bit). ICFD must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 4 ICFD 0 1 Description To clear ICFD, the CPU must read ICFD after it has been set to 1, then write a 0 in this bit (Initial value) This bit is set to 1 when an FTID input signal is received
Bit 3--Output Compare Flag A (OCFA): This status flag is set to 1 when the FRC value matches the OCRA value. This flag must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 3 OCFA 0 1 Description To clear OCFA, the CPU must read OCFA after it has been set to 1, then write a 0 in this bit (Initial value) This bit is set to 1 when FRC = OCRA
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Bit 2--Output Compare Flag B (OCFB): This status flag is set to 1 when the FRC value matches the OCRB value. This flag must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 2 OCFB 0 1 Description To clear OCFB, the CPU must read OCFB after it has been set to 1, then write a 0 in this bit (Initial value) This bit is set to 1 when FRC = OCRB
Bit 1--Timer Overflow Flag (OVF): This status flag is set to 1 when FRC overflows (changes from H'FFFF to H'0000). This flag must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 1 OVF 0 1 Description To clear OVF, the CPU must read OVF after it has been set to 1, then write a 0 in this bit (Initial value) This bit is set to 1 when FRC changes from H'FFFF to H'0000
Bit 0--Counter Clear A (CCLRA): This bit selects whether to clear FRC at compare-match A (when the FRC and OCRA values match).
Bit 0 CCLRA 0 1 Description The FRC is not cleared The FRC is cleared at compare-match A (Initial value)
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9.2.6
Bit
Timer Control Register (TCR)
7 IEDGA 6 IEDGB 0 R/W 5 IEDGC 0 R/W 4 IEDGD 0 R/W 3 BUFEA 0 R/W 2 BUFEB 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
Initial value Read/Write
0 R/W
TCR is an 8-bit readable/writable register that selects the rising or falling edge of the input capture signals, enables the input capture buffer mode, and selects the FRC clock source. TCR is initialized to H'00 by a reset and in the standby modes. Bit 7--Input Edge Select A (IEDGA): This bit selects the rising or falling edge of the input capture A signal (FTIA).
Bit 7 IEDGA 0 1 Description Input capture A events are recognized on the falling edge of FTIA Input capture A events are recognized on the rising edge of FTIA (Initial value)
Bit 6--Input Edge Select B (IEDGB): This bit selects the rising or falling edge of the input capture B signal (FTIB).
Bit 6 IEDGB 0 1 Description Input capture B events are recognized on the falling edge of FTIB Input capture B events are recognized on the rising edge of FTIB (Initial value)
Bit 5--Input Edge Select C (IEDGC): This bit selects the rising or falling edge of the input capture C signal (FTIC).
Bit 5 IEDGC 0 1 Description Input capture C events are recognized on the falling edge of FTIC Input capture C events are recognized on the rising edge of FTIC (Initial value)
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Bit 4--Input Edge Select D (IEDGD): This bit selects the rising or falling edge of the input capture D signal (FTID).
Bit 4 IEDGD 0 1 Description Input capture D events are recognized on the falling edge of FTID Input capture D events are recognized on the rising edge of FTID (Initial value)
Bit 3--Buffer Enable A (BUFEA): This bit selects whether to use ICRC as a buffer register for ICRA.
Bit 3 BUFEA 0 1 Description ICRC is used for input capture C ICRC is used as a buffer register for input capture A (Initial value)
Bit 2--Buffer Enable B (BUFEB): This bit selects whether to use ICRD as a buffer register for ICRB.
Bit 2 BUFEB 0 1 Description ICRD is used for input capture D ICRD is used as a buffer register for input capture B (Initial value)
Bits 1 and 0--Clock Select (CKS1 and CKS0): These bits select external clock input or one of three internal clock sources for FRC. External clock pulses are counted on the rising edge of external clock input pin FTCI.
Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 Description oP/2 internal clock source oP/8 internal clock source oP/32 internal clock source External clock source (rising edge) (Initial value)
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9.2.7
Bit
Timer Output Compare Control Register (TOCR)
7 -- 6 -- 1 -- 5 -- 1 -- 4 OCRS 0 R/W 3 OEA 0 R/W 2 OEB 0 R/W 1 OLVLA 0 R/W 0 OLVLB 0 R/W
Initial value Read/Write
1 --
TOCR is an 8-bit readable/writable register that enables output from the output compare pins, selects the output levels, and switches access between output compare registers A and B. TOCR is initialized to H'E0 by a reset and in the standby modes. Bits 7 to 5--Reserved: These bits cannot be modified and are always read as 1. Bit 4--Output Compare Register Select (OCRS): OCRA and OCRB share the same address. When this address is accessed, the OCRS bit selects which register is accessed. This bit does not affect the operation of OCRA or OCRB.
Bit 4 OCRS 0 1 Description OCRA is selected OCRB is selected (Initial value)
Bit 3--Output Enable A (OEA): This bit enables or disables output of the output compare A signal (FTOA).
Bit 3 OEA 0 1 Description Output compare A output is disabled Output compare A output is enabled (Initial value)
Bit 2--Output Enable B (OEB): This bit enables or disables output of the output compare B signal (FTOB).
Bit 2 OEB 0 1 Description Output compare B output is disabled Output compare B output is enabled (Initial value)
227
Bit 1--Output Level A (OLVLA): This bit selects the logic level to be output at the FTOA pin when the FRC and OCRA values match.
Bit 1 OLVLA 0 1 Description A 0 logic level is output for compare-match A A 1 logic level is output for compare-match A (Initial value)
Bit 0--Output Level B (OLVLB): This bit selects the logic level to be output at the FTOB pin when the FRC and OCRB values match.
Bit 0 OLVLB 0 1 Description A 0 logic level is output for compare-match B A 1 logic level is output for compare-match B (Initial value)
228
9.3
CPU Interface
The free-running counter (FRC), output compare registers (OCRA and OCRB), and input capture registers (ICRA to ICRD) are 16-bit registers, but they are connected to an 8-bit data bus. When the CPU accesses these registers, to ensure that both bytes are written or read simultaneously, the access is performed using an 8-bit temporary register (TEMP). These registers are written and read as follows: * Register Write When the CPU writes to the upper byte, the byte of write data is placed in TEMP. Next, when the CPU writes to the lower byte, this byte of data is combined with the byte in TEMP and all 16 bits are written in the register simultaneously. * Register Read When the CPU reads the upper byte, the upper byte of data is sent to the CPU and the lower byte is placed in TEMP. When the CPU reads the lower byte, it receives the value in TEMP. Programs that access these registers should normally use word access. Equivalently, they may access first the upper byte, then the lower byte by two consecutive byte accesses. Data will not be transferred correctly if the bytes are accessed in reverse order, or if only one byte is accessed. Figure 9.3 shows the data flow when FRC is accessed. The other registers are accessed in the same way. As an exception, when the CPU reads OCRA or OCRB, it reads both the upper and lower bytes directly, without using TEMP. Coding Examples To write the contents of general register R0 to OCRA: MOV.W To transfer the contents of ICRA to general register R0: MOV.W R0, @OCRA @ICRA, R0
229
Upper byte write Module data bus
CPU writes data H'AA
Bus interface
TEMP [H'AA]
FRCH [ ]
FRCL [ ]
Lower byte write
CPU writes data H'55
Bus interface
Module data bus
TEMP [H'AA]
FRCH [H'AA]
FRCL [H'55]
Figure 9.3a Write Access to FRC (when CPU Writes H'AA55)
230
Upper byte read
CPU reads data H'AA
Bus interface
Module data bus
TEMP [H'55]
FRCH [H'AA]
FRCL [H'55]
Lower byte read
CPU reads data H'55
Bus interface
Module data bus
TEMP [H'55]
FRCH [ ]
FRCL [ ]
Figure 9.3b Read Access to FRC (when FRC Contains H'AA55)
231
9.4
9.4.1
Operation
FRC Incrementation Timing
FRC increments on a pulse generated once for each period of the selected (internal or external) clock source. The clock source is selected by bits CKS0 and CKS1 in TCR. Internal Clock: The internal clock sources (oP/2, oP/8, oP/32) are created from the system clock (o) by a prescaler. FRC increments on a pulse generated from the falling edge of the prescaler output. See figure 9.4.
o
Internal clock FRC clock pulse
FRC
N-1
N
N+1
Figure 9.4 Increment Timing for Internal Clock Source
232
External Clock: If external clock input is selected, FRC increments on the rising edge of the FTCI clock signal. Figure 9.5 shows the increment timing. The pulse width of the external clock signal must be at least 1.5 system clock (o) periods. The counter will not increment correctly if the pulse width is shorter than 1.5 system clock periods.
o
FTCI
FRC clock pulse
FRC
N
N+1
Figure 9.5 Increment Timing for External Clock Source
233
9.4.2
Output Compare Timing
When a compare-match occurs, the logic level selected by the output level bit (OLVLA or OLVLB) in TOCR is output at the output compare pin (FTOA or FTOB). Figure 9.6 shows the timing of this operation for compare-match A.
o
FRC
N
N+1
N
N+1
OCRA Internal comparematch A signal
N
N
Clear* OLVLA
FTOA0
Note: * Cleared by software
Figure 9.6 Timing of Output Compare A
234
9.4.3
FRC Clear Timing
If the CCLRA bit in TCSR is set to 1, FRC is cleared when compare-match A occurs. Figure 9.7 shows the timing of this operation.
o
Internal comparematch A signal
FRC
N
H'0000
Figure 9.7 Clearing of FRC by Compare-Match A 9.4.4 Input Capture Timing
Input Capture Timing: An internal input capture signal is generated from the rising or falling edge of the signal at the input capture pin FTIx (x = A, B, C, D), as selected by the corresponding IEDGx bit in TCR. Figure 9.8 shows the usual input capture timing when the rising edge is selected (IEDGx = 1).
o
Input data FTI pin Internal input capture signal
Figure 9.8 Input Capture Timing (Usual Case) If the upper byte of ICRA/B/C/D is being read when the corresponding input capture signal arrives, the internal input capture signal is delayed by one state. Figure 9.9 shows the timing for this case.
235
Read cycle: CPU reads upper byte of ICR T1 o T2 T3
Input at FTI pin
Internal input capture signal
Figure 9.9 Input Capture Timing (1-State Delay due to ICRA/B/C/D Read) Buffered Input Capture Timing: ICRC and ICRD can operate as buffers for ICRA and ICRB. Figure 9.10 shows how input capture operates when ICRA and ICRC are used in buffer mode and IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDGA = 1 and IEDGC = 0), so that input capture is performed on both the rising and falling edges of FTIA.
o
FTIA
Internal input capture signal
FRC
n
n+1
N
N+1
ICRA
M
n
n
N
ICRC
m
M
M
n
Figure 9.10 Buffered Input Capture with Both Edges Selected
236
When ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the edge transition selected by the IEDGC bit occurs on the FTIC input capture line, ICFC will be set, and if the ICIEC bit is set, an interrupt will be requested. The FRC value will not be transferred to ICRC, however. In buffered input capture, if the upper byte of either of the two registers to which data will be transferred (ICRA and ICRC, or ICRB and ICRD) is being read when the input signal arrives, input capture is delayed by one system clock (o). Figure 9.11 shows the timing when BUFEA = 1.
Read cycle: CPU reads upper byte of ICRA or ICRC T1 o Input at FTIA pin Internal input capture signal T2 T3
Figure 9.11 Input Capture Timing (1-State Delay, Buffer Mode)
237
9.4.5
Timing of Input Capture Flag (ICF) Setting
The input capture flag ICFx (x = A, B, C, D) is set to 1 by the internal input capture signal. Figure 9.12 shows the timing of this operation.
o
Internal input capture signal
ICF
FRC
N
ICR
N
Figure 9.12 Setting of Input Capture Flag
238
9.4.6
Setting of Output Compare Flags A and B (OCFA and OCFB)
The output compare flags are set to "1" by an internal compare-match signal generated when the FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the last state in which the two values match, just before FRC increments to a new value. Accordingly, when the FRC and OCR values match, the compare-match signal is not generated until the next period of the clock source. Figure 9.13 shows the timing of the setting of the output compare flags.
o
FRC
N
N+1
OCRA or OCRB
N
Internal comparematch signal
OCFA or OCFB
Figure 9.13 Setting of Output Compare Flags
239
9.4.7
Setting of FRC Overflow Flag (OVF)
The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to H'0000). Figure 9.14 shows the timing of this operation.
o
FRC
H'FFFF
H'0000
Internal overflow signal OVF
Figure 9.14 Setting of Overflow Flag (OVF)
9.5
Interrupts
FRT0 can request seven interrupts: (three types): input capture A to D (ICIA, ICIB, ICIC, ICID), output compare A and B (OCIA and OCIB), and overflow (FOVI). Each interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the interrupt controller for each interrupt. Table 9.4 lists information about these interrupts. Table 9.4
Interrupt ICIA ICIB ICIC ICID OCIA OCIB FOVI
FRT0 Interrupts
Description Requested by ICFA Requested by ICFB Requested by ICFC Requested by ICFD Requested by OCFA Requested by OCFB Requested by OVF Low Priority High
240
9.6
Sample Application
In the example below, the free-running timer is used to generate two square-wave outputs with a 50% duty cycle and arbitrary phase relationship. The programming is as follows: 1. The CCLRA bit in TCSR is set to 1. 2. Each time a compare-match interrupt occurs, software inverts the corresponding output level bit in TOCR (OLVLA or OLVLB).
FRC H'FFFF OCRA OCRB H'0000 FTOA Clear counter
FTOB
Figure 9.15 Square-Wave Output (Example)
241
9.7
Application Notes
Application programmers should note that the following types of contention can occur in freerunning timer 0. Contention between FRC Write and Clear: If an internal counter clear signal is generated during the T3 state of a write cycle to the lower byte of the free-running counter, the clear signal takes priority and the write is not performed. Figure 9.16 shows this type of contention.
Write cycle: CPU write to lower byte of FRC T1 T2 T3
o
Internal address bus Internal write signal
FRC address
FRC clear signal
FRC
N
H'0000
Figure 9.16 FRC Write-Clear Contention
242
Contention between FRC Write and Increment: If an FRC increment pulse is generated during the T3 state of a write cycle to the lower byte of the free-running counter, the write takes priority and FRC is not incremented. Figure 9.17 shows this type of contention.
Write cycle: CPU write to lower byte of FRC T1 T2 T3
o
Internal address bus
FRC address
Internal write signal
FRC clock pulse
FRC
N
M Write data
Figure 9.17 FRC Write-Increment Contention
243
Contention between OCR Write and Compare-Match: If a compare-match occurs during the T3 state of a write cycle to the lower byte of OCRA or OCRB, the write takes priority and the compare-match signal is inhibited. Figure 9.18 shows this type of contention.
Write cycle: CPU write to lower byte of OCRA or OCRB T1 T2 T3
o
Internal address bus
OCR address
Internal write signal
FRC
N
N+1
OCRA or OCRB
N
M Write data
Compare-match A or B signal Inhibited
Figure 9.18 Contention between OCR Write and Compare-Match
244
Incrementation Caused by Changing of Internal Clock Source: When an internal clock source is changed, the changeover may cause FRC to increment. This depends on the time at which the clock select bits (CKS1 and CKS0) are rewritten, as shown in table 9.5. The pulse that increments FRC is generated at the falling edge of the internal clock source. If clock sources are changed when the old source is high and the new source is low, as in case number 3 in table 9.5, the changeover generates a falling edge that triggers the FRC increment clock pulse. Switching between an internal and external clock source can also cause FRC to increment. Table 9.5
No. 1
Effect of Changing Internal Clock Sources
Timing
Old clock source New clock source FRC clock pulse FRC N CKS rewrite N+1
Description Low low: CKS1 and CKS0 are rewritten while both clock sources are low.
2
Low high: CKS1 and CKS0 are rewritten while old clock source is low and new clock source is high.
Old clock source New clock source FRC clock pulse
FRC
N
N+1
N+2 CKS rewrite
245
Table 9.5
No. 3
Effect of Changing Internal Clock Sources (cont)
Timing
Old clock source
Description High low: CKS1 and CKS0 are rewritten while old clock source is high and new clock source is low.
New clock source * FRC clock pulse
FRC
N
N+1 CKS rewrite
N+2
4
High high: CKS1 and CKS0 are rewritten while both clock sources are high.
Old clock source
New clock source FRC clock pulse
FRC
N
N+1
N+2 CKS rewrite
Note: * The switching of clock sources is regarded as a falling edge that increments FRC.
246
Section 10 16-Bit Free-Running Timer 1
10.1 Overview
The H8/3318 has an on-chip 16-bit free-running timer (FRT) with two channels: FRT0 and FRT1. Each channel is based on a 16-bit free-running counter (FRC) and can generate two independent output waveforms, measure input pulse widths, or measure external clock periods. This section describes FRT1. For FRT0, see section 9, 16-Bit Free-Running Timer 0. The differences between FRT0 and FRT1 are that FRT0 has four input-capture lines and four input-capture interrupt sources, and allows buffering to be designated. FRT1 has only one inputcapture line and one input-capture interrupt source, and does not support buffering. 10.1.1 Features
The features of FRT1 are listed below. * Selection of four clock sources The free-running counter can be driven by an internal clock source (oP/2, oP/8, or oP/32), or an external clock input (enabling use as an external event counter). * Two independent comparators Each comparator can generate an independent waveform. * Input capture The current count can be captured on the rising or falling edge (selectable) of an input signal. * Counter can be cleared under program control The free-running counter can be cleared on compare-match A. * Four interrupt sources Compare-match A and B, input capture, and overflow interrupts are requested independently.
247
10.1.2
Block Diagram
Figure 10.1 shows a block diagram of free-running timer 1.
Internal clock sources External clock source FTCI Clock select oP/2 oP/8 oP/32 Clock Comparematch A OCRA (H/L)
Comparator A
FTOA1 FTOB1 FTI
Overflow Clear Comparator B Module data bus Bus interface FRC (H/L)
Internal data bus
Comparematch B Control logic
OCRB (H/L)
Capture
ICR (H/L)
TCSR
TCR
ICI OCIA OCIB FOVI Interrupt signals Legend OCRA: OCRB: FRC: ICR: TCSR: TCR: Output compare register A Output compare register B Free-running counter Input capture register Timer control/status register Timer control register
Figure 10.1 Block Diagram of 16-Bit Free-Running Timer 1
248
10.1.3
Input and Output Pins
Table 10.1 lists the input and output pins of free-running timer 1. Table 10.1 FRT1 Input and Output Pins
Name Counter clock input Output compare A Output compare B Input capture Abbreviation FTCI FTOA1* FTOB1* FTI I/O Input Output Output Input Function Input of external free-running counter clock signal Output controlled by comparator A Output controlled by comparator B Input capture trigger
Note: * In this manual, the channel subscripts are normally omitted.
10.1.4
Register Configuration
Table 10.2 lists the registers of free-running timer 1. Table 10.2 Register Configuration
Name Timer control register Timer control/status register Free-running counter (high) Free-running counter (low) Output compare register A (high) Output compare register A (low) Output compare register B (high) Output compare register B (low) Input capture register (high) Input capture register (low) Abbreviation TCR TCSR FRC (H) FRC (L) OCRA (H) OCRA (L) OCRB (H) OCRB (L) ICR (H) ICR (L) R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R R Initial Value H'00 H'00 H'00 H'00 H'FF H'FF H'FF H'FF H'00 H'00 Address H'FFA0 H'FFA1 H'FFA2 H'FFA3 H'FFA4 H'FFA5 H'FFA6 H'FFA7 H'FFA8 H'FFA9
Note: * Software can write a 0 to clear bits 7 to 4, but cannot write a 1 in these bits.
249
10.2
10.2.1
Bit
Register Descriptions
Free-Running Counter (FRC)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value Read/Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
FRC is a 16-bit readable/writable up-counter that increments on an internal pulse generated from a clock source. The clock source is selected by the clock select 1 and 0 bits (CKS1 and CKS0) of the timer control register (TCR). When FRC overflows from H'FFFF to H'0000, the overflow flag (OVF) in the timer control/status register (TCSR) is set to 1. Because FRC is a 16-bit register, a temporary register (TEMP) is used when the FRC is written or read. See section 10.3, CPU Interface, for details. FRC is initialized to H'0000 by a reset and in the standby modes. It can also be cleared by compare-match A. 10.2.2
Bit
Output Compare Registers A and B (OCRA and OCRB)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value Read/Write
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
OCRA and OCRB are 16-bit readable/writable registers, the contents of which are continually compared with the value in FRC. When a match is detected, the corresponding output compare flag (OCFA or OCFB) is set in the timer control/status register (TCSR). In addition, if the output enable bit (OEA or OEB) in the timer control register (TCR) is set to 1, when the output compare register and FRC values match, the logic level selected by the output level bit (OLVLA or OLVLB) in TCSR is output at the output compare pin (FTOA1 or FTOB1). Following a reset, the FTOA1 and FTOB1 output levels are 0 until the first compare-match. Because OCRA and OCRB are 16-bit registers, a temporary register (TEMP) is used for write access, as explained in section 10.3, CPU Interface. OCRA and OCRB are initialized to H'FFFF by a reset and in the standby modes.
250
10.2.3
Bit
Input Capture Register (ICR)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value Read/Write
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
ICR is a 16-bit read-only register. When the rising or falling edge of the signal at the input capture pin (FTI) is detected, the current FRC value is copied to ICR. At the same time, the input capture flag (ICF) in the timer control/status register (TCSR) is set to 1. The input capture edge is selected by the input edge select bit (IEDG) in TCSR. Because ICR is a 16-bit register, a temporary register (TEMP) is used when it is read. See Section 10.3, CPU Interface, for details. To ensure input capture, the width of the input capture pulse should be at least 1.5 system clock cycles (1.5*o). ICR is initialized to H'0000 by a reset and in the standby modes. Note: When input capture is detected, the FRC value is transferred to ICR even if the input capture flag is already set. 10.2.4
Bit
Timer Control Register (TCR)
7 ICIE 6 OCIBE 0 R/W 5 OCICE 0 R/W 4 OVIE 0 R/W 3 OEB 0 R/W 2 OEA 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
Initial value Read/Write
0 R/W
TCR is an 8-bit readable/writable register that enables and disables output signals and interrupts, and selects the timer clock source. TCR is initialized to H'00 by a reset and in the standby modes.
251
Bit 7--Input Capture Interrupt Enable (ICIE): Selects whether to request an input capture interrupt (ICI) when the input capture flag (ICF) in the timer status/control register (TCSR) is set to 1.
Bit 7 ICIE 0 1 Description Input capture interrupt request (ICI) is disabled Input capture interrupt request (ICI) is enabled (Initial value)
Bit 6--Output Compare Interrupt Enable B (OCIEB): Selects whether to request output compare interrupt B (OCIB) when output compare flag B (OCFB) in TCSR is set to 1.
Bit 6 OCIEB 0 1 Description Output compare interrupt request B (OCIB) is disabled Output compare interrupt request B (OCIB) is enabled (Initial value)
Bit 5--Output Compare Interrupt Enable A (OCIEA): Selects whether to request output compare interrupt A (OCIA) when output compare flag A (OCFA) in TCSR is set to 1.
Bit 5 OCIEA 0 1 Description Output compare interrupt request A (OCIA) is disabled Output compare interrupt request A (OCIA) is enabled (Initial value)
Bit 4--Timer Overflow Interrupt Enable (OVIE): Selects whether to request an overflow interrupt (FOVI) when the timer overflow flag (OVF) in TCSR is set to 1.
Bit 4 OVIE 0 1 Description Timer overflow interrupt request (FOVI) is disabled Timer overflow interrupt request (FOVI) is enabled (Initial value)
Bit 3--Output Enable B (OEB): Enables or disables output of the output compare B signal (FTOB). If output compare B is enabled, the FTOB1 pin is driven to the level selected by OLVLB in TCSR whenever the FRC value matches the value in output compare register B (OCRB).
252
Bit 3 OEB 0 1
Description Output compare B output is disabled Output compare B output is enabled (Initial value)
Bit 2--Output Enable A (OEA): Enables or disables output of the output compare A signal (FTOA). If output compare A is enabled, the FTOA pin is driven to the level selected by OLVLA in the timer status/control register (TCSR) whenever the FRC value matches the value in output compare register A (OCRA).
Bit 2 OEA 0 1 Description Output compare A output is disabled Output compare A output is enabled (Initial value)
Bits 1 and 0--Clock Select (CKS1 and CKS0): These bits select external clock input or one of three internal clock sources for the FRC. External clock pulses are counted on the rising edge of external clock input pin FTCI.
Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 Description oP/2 internal clock source oP/8 internal clock source oP/32 internal clock source External clock source (rising edge) (Initial value)
10.2.5
Bit
Timer Control/Status Register (TCSR)
7 ICA 6 OCFB 0 R/(W)* 5 OCFA 0 R/(W)* 4 OVF 0 R/(W)* 3 OLVLB 0 R/(W) 2 OLVLA 0 R/(W) 1 IEDG 0 R/(W) 0 CCLRA 0 R/(W)
Initial value Read/Write
0 R/(W)*
Note: * Software can write a 0 in bits 7 to 4 to clear the flags, but cannot write a 1 in these bits.
TCSR is an 8-bit readable and partially writable register that contains the four interrupt flags and selects the output compare levels, input capture edge, and whether to clear the counter on compare-match A. TCSR is initialized to H'00 by a reset and in the standby modes.
253
Bit 7--Input Capture Flag (ICF): This status bit is set to 1 to flag an input capture event, indicating that the FRC value has been copied to ICR. ICF must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 7 ICF 0 1 Description To clear ICF, the CPU must read ICF after it has been set to 1, then write a 0 in this bit (Initial value) This bit is set to 1 when an input capture signal causes the FRC value to be copied to the ICR
Bit 6--Output Compare Flag B (OCFB): This status flag is set to 1 when the FRC value matches the OCRB value. This flag must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 6 OCFB 0 1 Description To clear OCFB, the CPU must read OCFB after it has been set to 1, then write a 0 in this bit (Initial value) This bit is set to 1 when FRC = OCRB
Bit 5--Output Compare Flag A (OCFA): This status flag is set to 1 when the FRC value matches the OCRA value. This flag must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 5 OCFA 0 1 Description To clear OCFA, the CPU must read OCFA after it has been set to 1, then write a 0 in this bit (Initial value) This bit is set to 1 when FRC = OCRA
Bit 4--Timer Overflow Flag (OVF): This status flag is set to 1 when the FRC overflows (changes from H'FFFF to H'0000). This flag must be cleared by software. It is set by hardware, however, and cannot be set by software.
254
Bit 4 OVF 0 1
Description To clear OVF, the CPU must read OVF after it has been set to 1, then write a 0 in this bit (Initial value) This bit is set to 1 when FRC changes from H'FFFF to H'0000
Bit 3--Output Level B (OLVLB): Selects the logic level output at the FTOB pin when the FRC and OCRB values match.
Bit 3 OLVLB 0 1 Description A 0 logic level is output for compare-match B A 1 logic level is output for compare-match B (Initial value)
Bit 2--Output Level A (OLVLA): Selects the logic level output at the FTOA pin when the FRC and OCRA values match.
Bit 2 OLVLA 0 1 Description A 0 logic level is output for compare-match A A 1 logic level is output for compare-match A (Initial value)
Bit 1--Input Edge Select (IEDG): Selects the rising or falling edge of the input capture signal (FTI).
Bit 1 IEDG 0 1 Description FRC contents are transferred to ICR on the falling edge of FTI FRC contents are transferred to ICR on the rising edge of FTI (Initial value)
Bit 0--Counter Clear A (CCLRA): Selects whether to clear FRC at compare-match A (when the FRC and OCRA values match).
Bit 0 CCLRA 0 1 Description The FRC is not cleared The FRC is cleared at compare-match A (Initial value)
255
10.3
CPU Interface
The free-running counter (FRC), output compare registers (OCRA and OCRB), and input capture register (ICR) are 16-bit registers, but they are connected to an 8-bit data bus. When the CPU accesses these registers, to ensure that both bytes are written or read simultaneously, the access is performed using an 8-bit temporary register (TEMP). These registers are written and read as follows: * Register Write When the CPU writes to the upper byte, the byte of write data is placed in TEMP. Next, when the CPU writes to the lower byte, this byte of data is combined with the byte in TEMP and all 16 bits are written in the register simultaneously. * Register Read When the CPU reads the upper byte, the upper byte of data is sent to the CPU and the lower byte is placed in TEMP. When the CPU reads the lower byte, it receives the value in TEMP. Programs that access these registers should normally use word access. Equivalently, they may access first the upper byte, then the lower byte by two consecutive byte accesses. Data will not be transferred correctly if the bytes are accessed in reverse order, if only one byte is accessed. Coding Examples To write the contents of general register R0 to OCRA: MOV.W To transfer the ICR contents to general register R0: MOV.W R0, @OCRA @ICR, R0
Figure 10.2 shows the data flow when FRC is accessed. The other registers are accessed in the same way. As an exception, when the CPU reads OCRA or OCRB, it reads both the upper and lower bytes directly, without using TEMP.
256
Upper byte write Module data bus
CPU writes data H'AA
Bus interface
TEMP [H'AA]
FRCH [ ]
FRCL [ ]
Lower byte write
CPU writes data H'55
Bus interface
Module data bus
TEMP [H'AA]
FRCH [H'AA]
FRCL [H'55]
Figure 10.2a Write Access to FRC (When CPU Writes H'AA55)
257
Upper byte read
CPU writes data H'AA
Bus interface
Module data bus
TEMP [H'55]
FRCH [H'AA]
FRCL [H'55]
Lower byte read
CPU writes data H'55
Bus interface
Module data bus
TEMP [H'55]
FRCH [ ]
FRCL [ ]
Figure 10.2b Read Access to FRC (When FRC Contains H'AA55)
258
10.4
10.4.1
Operation
FRC Incrementation Timing
FRC increments on a pulse generated once for each cycle of the selected (internal or external) clock source. Internal Clock Sources: Can be selected by the CKS1 and CKS0 bits in the TCR. Internal clock sources are created by dividing the system clock (o). Three internal clock sources are available: oP/2, oP/8, and oP/32. Figure 10.3 shows the increment timing.
o
Prescaler output FRC clock pulse
FRC
N-1
N
N+1
Figure 10.3 Increment Timing for Internal Clock Source
259
External Clock Input: Can be selected by the CKS1 and CKS0 bits in the TCR. The FRC increments on the rising edge of the FTCI clock signal. The pulse width of the external clock signal must be at least 1.5 system clock (o) cycles. The counter will not increment correctly if the pulse width is shorter than this. Figure 10.4 shows the increment timing.
o
FTCI
FRC clock pulse
FRC
N
N+1
Figure 10.4 Increment Timing for External Clock Source
260
10.4.2
Output Compare Timing
When a compare-match occurs, the logic level selected by the output level bit (OLVLA or OLVLB) in the TCSR is output at the output compare pin (FTOA or FTOB). Figure 10.5 shows the timing of this operation for compare-match A.
o
Internal comparematch A signal Clear* OLVLA
FTOA
Note: * Cleared by software
Figure 10.5 Timing of Output Compare A 10.4.3 FRC Clear Timing
If the CCLRA bit in the TCSR is set to 1, the FRC is cleared when compare-match A occurs. Figure 10.6 shows the timing of this operation.
o
Internal comparematch A signal
FRC
N
H'0000
Figure 10.6 Clearing of FRC by Compare-Match A
261
10.4.4
Input Capture Timing
An internal input capture signal is generated from the rising or falling edge of the FTI input, as selected by the IEDG bit in TCSR. Figure 10.7 shows the usual input capture timing when the rising edge is selected (IEDG = 1).
o
Input at FTI pin
Internal input capture signal
Figure 10.7 Input Capture Timing (Usual Case) If the upper byte of ICR is being read when the internal input capture signal should be generated, the internal input capture signal is delayed by one state. Figure 10.8 shows the timing for this case.
ICR upper byte read cycle T1 o T2 T3
Input at FTI pin
Internal input capture signal
Figure 10.8 Input Capture Timing (1-State Delay Due to ICR Read)
262
10.4.5
Timing of Input Capture Flag (ICF) Setting
The input capture flag ICF is set to 1 by the internal input capture signal. The FRC contents are transferred to ICR at the same time. Figure 10.9 shows the timing of this operation.
o
Internal input capture signal
ICF
FRC
N
ICR
N
Figure 10.9 Setting of Input Capture Flag 10.4.6 Setting of FRC Overflow Flag (OVF)
The FRC overflow flag (OVF) is set to 1 when FRC changes from H'FFFF to H'0000. Figure 10.10 shows the timing of this operation.
o
FRC
H'FFFF
H'0000
Internal overflow signal OVF
Figure 10.10 Setting of Overflow Flag (OVF)
263
10.5
Interrupts
FRT1 can request four interrupts: input capture (ICI), output compare A and B (OCIA and OCIB), and overflow (FOVI). Each interrupt can be enabled or disabled by an enable bit in TCR. Independent signals are sent to the interrupt controller for each interrupt. Table 10.3 lists information about these interrupts. Table 10.3 FRT1 Interrupts
Interrupt ICI OCIA OCIB FOVI Description Requested by ICF Requested by OCFA Requested by OCFB Requested by OVF Low Priority High
10.6
Sample Application
In the example below, the free-running timer channel is used to generate two square-wave outputs with a 50% duty cycle and arbitrary phase relationship. The programming is as follows: 1. The CCLRA bit in TCSR is set to 1. 2. Each time a compare-match interrupt occurs, software inverts the corresponding output level bit in TCSR (OLVLA or OLVLB).
FRC H'FFFF OCRA OCRB H'0000 FTOA1 Clear counter
FTOB1
Figure 10.11 Square-Wave Output (Example)
264
10.7
Application Notes
Application programmers should note that the following types of contention can occur in freerunning timer 1. Contention between FRC Write and Clear: If an internal counter clear signal is generated during the T3 state of a write cycle to the lower byte of the free-running counter, the clear signal takes priority and the write is not performed. Figure 10.12 shows this type of contention.
FRC lower byte write cycle T1 T2 T3
o
Internal address bus Internal write signal
FRC address
FRC clear signal
FRC
N
H'0000
Figure 10.12 FRC Write-Clear Contention
265
Contention between FRC Write and Increment: If an FRC increment pulse is generated during the T3 state of a write cycle to the lower byte of the free-running counter, the write takes priority and FRC is not incremented. Figure 10.13 shows this type of contention.
FRC lower byte write cycle T1 T2 T3
o
Internal address bus
FRC address
Internal write signal
FRC clock pulse
FRC
N
M Write data
Figure 10.13 FRC Write-Increment Contention
266
Contention between OCR Write and Compare-Match: If a compare-match occurs during the T3 state of a write cycle to the lower byte of OCRA or OCRB, the write takes precedence and the compare-match signal is inhibited. Figure 10.14 shows this type of contention.
OCRA or OCRB lower byte write cycle T1 T2 T3
o
Internal address bus
OCR address
Internal write signal
FRC
N
N+1
OCRA or OCRB
N
M Write data
Compare-match A or B signal Inhibited
Figure 10.14 Contention between OCR Write and Compare-Match
267
Incrementation Caused by Changing of Internal Clock Source: When an internal clock source is changed, the changeover may cause FRC to increment. This depends on the time at which the clock select bits (CKS1 and CKS0) are rewritten, as shown in table 10.4. The pulse that increments FRC is generated at the falling edge of the internal clock source. If clock sources are changed when the old source is high and the new source is low, as in case number 3 in table 10.4, the changeover generates a falling edge that triggers the FRC increment clock pulse. Switching between an internal and external clock source can also cause FRC to increment. Table 10.4 Effect of Changing Internal Clock Sources
No. 1 Description Low low: CKS1 and CKS0 are rewritten while both clock sources are low. Timing
Old clock source New clock source FRC clock pulse FRC N CKS rewrite N+1
2
Low high: CKS1 and CKS0 are rewritten while old clock source is low and new clock source is high.
Old clock source New clock source FRC clock pulse
FRC
N
N+1
N+2 CKS rewrite
268
Table 10.4 Effect of Changing Internal Clock Sources (cont)
No. 3 Description High low: CKS1 and CKS0 are rewritten while old clock source is high and new clock source is low. Timing
Old clock source
New clock source * FRC clock pulse
FRC
N
N+1 CKS rewrite
N+2
4
High high: CKS1 and CKS0 are rewritten while both clock sources are high.
Old clock source
New clock source FRC clock pulse
FRC
N
N+1
N+2 CKS rewrite
Note: * The switching of clock sources is regarded as a falling edge that increments FRC.
269
Section 11 8-Bit Timers
11.1 Overview
The H8/3318 includes an 8-bit timer module with two channels (numbered 0 and 1). Each channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that are constantly compared with the TCNT value to detect compare-match events. One of the many applications of the 8-bit timer module is to generate a rectangular-wave output with an arbitrary duty cycle. 11.1.1 Features
The features of the 8-bit timer module are listed below. * Selection of seven clock sources The counters can be driven by one of six internal clock signals or an external clock input (enabling use as an external event counter). * Selection of three ways to clear the counters The counters can be cleared on compare-match A or B, or by an external reset signal. * Timer output controlled by two time constants The timer output signal in each channel is controlled by two independent time constants, enabling the timer to generate output waveforms with an arbitrary duty cycle. PWM waveforms with a duty cycle of 0 to 100% can easily be output by selecting PWM mode. * Three independent interrupts Compare-match A and B and overflow interrupts can be requested independently.
271
11.1.2
Block Diagram
Figure 11.1 shows a block diagram of one channel in the 8-bit timer module.
Internal clock sources
External clock source TMCI
Channel 0 oP/2 oP/8 oP/32 oP/64 oP/256 oP/1024 Clock
Channel 1 oP/2 oP/8 oP/64 oP/128 oP/1024 oP/2048
Clock select
TCORA
Compare-match A Comparator A TMO TMRI Clear Comparator B Control logic Compare-match B TCORB Overflow Module data bus TCNT Internal data bus
TCSR
TCR CMIA CMIB OVI Interrupt signals Legend TCORA: TCORB: TCNT: TCSR: TCR:
Time constant register A (8 bits) Time constant register B (8 bits) Timer counter Timer control status register (8 bits) Timer control register (8 bits)
Figure 11.1 Block Diagram of 8-Bit Timer (1 Channel)
272
Bus interface
11.1.3
Input and Output Pins
Table 11.1 lists the input and output pins of the 8-bit timer. Table 11.1 Input and Output Pins of 8-Bit Timer
Channel 0 Name Timer output Timer clock input Timer reset input 1 Timer output Timer clock input Timer reset input Abbr.* TMO0 TMCI0 TMRI0 TMO1 TMCI1 TMRI1 I/O Output Input Input Output Input Input Function Output controlled by compare-match External clock source for the counter External reset signal for the counter Output controlled by compare-match External clock source for the counter External reset signal for the counter
Note: * In this manual, the channel subscripts are normally omitted.
11.1.4
Register Configuration
Table 11.2 lists the registers of the 8-bit timer module. Table 11.2 8-Bit Timer Registers
Channel 0 Name Timer control register Timer control/status register Timer constant register A Timer constant register B Timer counter 1 Timer control register Timer control/status register Timer constant register A Timer constant register B Timer counter 0 and 1 Serial/timer control register Abbreviation TCR TCSR TCORA TCORB TCNT TCR TCSR TCORA TCORB TCNT STCR R/W R/W R/(W)* R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W Initial Value H'00 H'00 H'FF H'FF H'00 H'00 H'00 H'FF H'FF H'00 H'1C Address H'FFC8 H'FFC9 H'FFCA H'FFCB H'FFCC H'FFD0 H'FFD1 H'FFD2 H'FFD3 H'FFD4 H'FFC3
Note: * Software can write a 0 to clear bits 7 to 5, but cannot write a 1 in these bits.
273
11.2
11.2.1
Bit
Register Descriptions
Timer Counter (TCNT)
7 6 5 4 3 2 1 0
Initial value Read/Write
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Each timer counter (TCNT) is an 8-bit up-counter that increments on a pulse generated from an internal or external clock source selected by clock select bits 2 to 0 (CKS2 to CKS0) of the timer control register (TCR). The CPU can always read or write the timer counter. The timer counter can be cleared by an external reset input or by an internal compare-match signal generated at a compare-match event. Clock clear bits 1 and 0 (CCLR1 and CCLR0) of the timer control register select the method of clearing. When a timer counter overflows from H'FF to H'00, the overflow flag (OVF) in the timer control/status register (TCSR) is set to 1. The timer counters are initialized to H'00 by a reset and in the standby modes. 11.2.2
Bit
Time Constant Registers A and B (TCORA and TCORB)
7 6 5 4 3 2 1 0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
TCORA and TCORB are 8-bit readable/writable registers. The timer count is continually compared with the constants written in these registers (except during the T3 state of a write cycle to TCORA or TCORB). When a match is detected, the corresponding compare-match flag (CMFA or CMFB) is set in the timer control/status register (TCSR). The timer output signal is controlled by these compare-match signals as specified by output select bits 3 to 0 (OS3 to OS0) in the timer control/status register (TCSR). TCORA and TCORB are initialized to H'FF by a reset and in the standby modes.
274
11.2.3
Bit
Timer Control Register (TCR)
7 CMIEB 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W 3 CCLR0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
Initial value Read/Write
0 R/W
TCR is an 8-bit readable/writable register that selects the clock source and the time at which the timer counter is cleared, and enables interrupts. TCR is initialized to H'00 by a reset and in the standby modes. For timing diagrams, see section 11.3, Operation. Bit 7--Compare-match Interrupt Enable B (CMIEB): This bit selects whether to request compare-match interrupt B (CMIB) when compare-match flag B (CMFB) in the timer control/status register (TCSR) is set to 1.
Bit 7 CMIEB 0 1 Description Compare-match interrupt request B (CMIB) is disabled Compare-match interrupt request B (CMIB) is enabled (Initial value)
Bit 6--Compare-match Interrupt Enable A (CMIEA): This bit selects whether to request compare-match interrupt A (CMIA) when compare-match flag A (CMFA) in TCSR is set to 1.
Bit 6 CMIEA 0 1 Description Compare-match interrupt request A (CMIA) is disabled Compare-match interrupt request A (CMIA) is enabled (Initial value)
Bit 5--Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a timer overflow interrupt (OVI) when the overflow flag (OVF) in TCSR is set to 1.
Bit 5 OVIE 0 1 Description The timer overflow interrupt request (OVI) is disabled The timer overflow interrupt request (OVI) is enabled (Initial value)
275
Bits 4 and 3--Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select how the timer counter is cleared: by compare-match A or B or by an external reset input (TMRI).
Bit 4 CCLR1 0 Bit 3 CCLR0 0 1 1 0 1 Description Not cleared Cleared on compare-match A Cleared on compare-match B Cleared on rising edge of external reset input signal (Initial value)
Bits 2, 1, and 0--Clock Select (CKS2, CKS1, and CKS0): These bits and bits ICKS1 and ICKS0 in the serial/timer control register (STCR) select the internal or external clock source for the timer counter. Six internal clock sources, derived by prescaling the system clock, are available for each timer channel. For internal clock sources the counter is incremented on the falling edge of the internal clock. For an external clock source, these bits can select whether to increment the counter on the rising or falling edge of the clock input (TMCI), or on both edges.
276
TCR Channel 0 Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 1 1 1 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 0 1
STCR Bit 1 Bit 0 ICKS1 ICKS0 Description -- -- -- -- -- -- -- -- -- -- -- -- 0 1 0 1 0 1 -- -- -- -- -- 0 1 0 1 0 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- No clock source (timer stopped) (Initial value) oP/8 internal clock, counted on falling edge oP/2 internal clock, counted on falling edge oP/64 internal clock, counted on falling edge oP/32 internal clock, counted on falling edge oP/1024 internal clock, counted on falling edge oP/256 internal clock, counted on falling edge No clock source (timer stopped) External clock source, counted on rising edge External clock source, counted on falling edge External clock source, counted on both rising and falling edges No clock source (timer stopped) (Initial value) oP/8 internal clock, counted on falling edge oP/2 internal clock, counted on falling edge oP/64 internal clock, counted on falling edge oP/128 internal clock, counted on falling edge oP/1024 internal clock, counted on falling edge oP/2048 internal clock, counted on falling edge No clock source (timer stopped) External clock source, counted on rising edge External clock source, counted on falling edge External clock source, counted on both rising and falling edges
277
11.2.4
Bit
Timer Control/Status Register (TCSR)
7 CMFB 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 PWME 0 R/W 3 OS3 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W
Initial value Read/Write
0 R/(W)*
Note: * Software can write a 0 in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits.
TCSR is an 8-bit readable and partially writable register that indicates compare-match and overflow status and selects the effect of compare-match events on the timer output signal. TCSR is initialized to H'00 by a reset and in the standby modes. Bit 7--Compare-Match Flag B (CMFB): This status flag is set to 1 when the timer count matches the time constant set in TCORB. CMFB must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 7 CMFB 0 1 Description To clear CMFB, the CPU must read CMFB after it has been set to 1, then write a 0 in this bit (Initial value) This bit is set to 1 when TCNT = TCORB
Bit 6--Compare-Match Flag A (CMFA): This status flag is set to 1 when the timer count matches the time constant set in TCORA. CMFA must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 6 CMFA 0 1 Description To clear CMFA, the CPU must read CMFA after it has been set to 1, then write a 0 in this bit (Initial value) This bit is set to 1 when TCNT = TCORA
Bit 5--Timer Overflow Flag (OVF): This status flag is set to 1 when the timer count overflows (changes from H'FF to H'00). OVF must be cleared by software. It is set by hardware, however, and cannot be set by software.
278
Bit 5 OVF 0 1
Description To clear OVF, the CPU must read OVF after it has been set to 1, then write a 0 in this bit (Initial value) This bit is set to 1 when TCNT changes from H'FF to H'00
Bit 4--PWM Mode Enable (PWME): This bit selects PWM mode for the timer output.
Bit 4 PWME 0 1 Description Normal timer mode PWM mode (Initial value)
In PWM mode, CCLR1 to CCLR0 and OS3 to OS0 must be set so that the timer output cycle is determined by the contents of TCORA, and the timer output duty cycle by the contents of TCORB. In this case, the timer output pulse cycle, pulse width, and duty cycle conform to the following expressions. If TCORA < TCORB, the output is saturated at a 100% duty cycle. When TCORB TCORA: Timer output pulse cycle = selected internal clock cycle x (TCORA + 1) Timer output pulse width = selected internal clock cycle x TCORB Timer output duty cycle = TCORB / (TCORA + 1)
TCR PWM Output Mode Direct output (when the above timer pulse width is high) Inverted output (when the above timer pulse width is low) CCLR1 0 0 CCLR0 1 1 OS3 0 1
TCSR OS2 1 0 OS1 1 0 OS0 0 1
In PWM mode, a buffer register is inserted between TCORB and the module data bus, and the data written to TCORB is held in the buffer register until a TCORA compare-match occurs. This makes it easy to obtain PWM output with no disruption of the waveform. As regards the timer output specification made by OS3 to OS0, the priority of a change due to compare-match B is higher. Care is required since the operation is different from that in the normal timer mode. Bits 3 to 0--Output Select 3 to 0 (OS3 to OS0): These bits specify the effect of TCOR-TCNT compare-match events on the timer output signal (TMO). Bits OS3 and OS2 control the effect of compare-match B on the output level. Bits OS1 and OS0 control the effect of compare-match A on the output level.
279
If compare-match A and B occur simultaneously, any conflict is resolved according to the following priority order: toggle > 1 output > 0 output. After a reset, the timer output is 0 until the first compare-match event. When all four output select bits are cleared to 0 the timer output signal is disabled.
Bit 3 OS3 0 Bit 2 OS2 0 1 1 0 1 Description No change when compare-match B occurs Output changes to 0 when compare-match B occurs Output changes to 1 when compare-match B occurs Output inverts (toggles) when compare-match B occurs (Initial value)
Bit 1 OS1 0
Bit 0 OS0 0 1
Description No change when compare-match A occurs Output changes to 0 when compare-match A occurs Output changes to 1 when compare-match A occurs Output inverts (toggles) when compare-match A occurs (Initial value)
1
0 1
11.2.5
Bit
Serial/Timer Control Register (STCR)
7 RING 6 CMPF 0 R/(W)* 5 CMPIE 0 R/W 4 LOAD 1 (W) 3 MARK 1 (W) 2 -- 1 -- 1 ICKS1 0 R/W 0 ICKS0 0 R/W
Initial value Read/Write
0 R/W
Note: * Software can write a 0 in bit 6 to clear the flags, but cannot write a 1 in this bit.
STCR is an 8-bit readable/writable register that controls the serial communication interface, selects clock sources for the timer counters, and controls DTU channel B. STCR is initialized to H'1C by a reset. Bits 7 to 3--DTU Channel B Control: These bits control DTU channel B. For details, see section 5, Data Transfer Unit. Bit 2--Reserved: This bit cannot be modified, and is always read as 1.
280
Bits 1 and 0--Internal Clock Source Select 1 and 0 (ICKS1 and ICKS0): These bits and bits CKS2 to CKS0 in the TCR select clock sources for the timer counters. For details, see section 11.2.3, Timer Control Register.
11.3
11.3.1
Operation
TCNT Incrementation Timing
The timer counter increments on a pulse generated once for each period of the selected (internal or external) clock source. Internal Clock: Internal clock sources are created from the system clock by a prescaler. The counter increments on an internal TCNT clock pulse generated from the falling edge of the prescaler output, as shown in figure 11.2. Bits CKS2 to CKS0 of TCR and bits ICKS1 and ICKS0 of STCR can select one of the six internal clocks.
o
Internal clock TCNT clock pulse
TCNT
N-1
N
N+1
Figure 11.2 Count Timing for Internal Clock Input
281
External Clock: If external clock input (TMCI) is selected, the timer counter can increment on the rising edge, the falling edge, or both edges of the external clock signal. Figure 11.3 shows incrementation on both edges of the external clock signal. The external clock pulse width must be at least 1.5 system clock periods for incrementation on a single edge, and at least 2.5 system clock periods for incrementation on both edges. The counter will not increment correctly if the pulse width is shorter than these values.
o
External clock source TMCI TCNT clock pulse
TCNT
N-1
N
N+1
Figure 11.3 Count Timing for External Clock Input
282
11.3.2
Compare-Match Timing
Setting of Compare-Match Flags A and B (CMFA and CMFB): The compare-match flags are set to 1 by an internal compare-match signal generated when the timer count matches the time constant in TCORA or TCORB. The compare-match signal is generated at the last state in which the match is true, just before the timer counter increments to a new value. Accordingly, when the timer count matches one of the time constants, the compare-match signal is not generated until the next period of the clock source. Figure 11.4 shows the timing of the setting of the compare-match flags.
o
TCNT
N
N+1
TCOR
N
Internal comparematch signal
CMF
Figure 11.4 Setting of Compare-Match Flags
283
Output Timing: When a compare-match event occurs, the timer output changes as specified by the output select bits (OS3 to OS0) in TCSR. Depending on these bits, the output can remain the same, change to 0, change to 1, or toggle. Figure 11.5 shows the timing when the output is set to toggle on compare-match A.
o
Internal comparematch A signal Timer output (TMO)
Figure 11.5 Timing of Timer Output Timing of Compare-Match Clear: Depending on the CCLR1 and CCLR0 bits in TCR, the timer counter can be cleared when compare-match A or B occurs. Figure 11.6 shows the timing of this operation.
o
Internal comparematch signal
TCNT
N
H'00
Figure 11.6 Timing of Compare-Match Clear
284
11.3.3
External Reset of TCNT
When the CCLR1 and CCLR0 bits in TCR are both set to 1, the timer counter is cleared on the rising edge of an external reset input. Figure 11.7 shows the timing of this operation. The timer reset pulse width must be at least 1.5 system clock periods.
o
External reset input (TMRI) Internal clear pulse TCNT N-1 N H'00
Figure 11.7 Timing of External Reset 11.3.4 Setting of TCSR Overflow Flag (OVF)
The overflow flag (OVF) is set to 1 when the timer count overflows (changes from H'FF to H'00). Figure 11.8 shows the timing of this operation.
o
TCNT
H'FF
H'00
Internal overflow signal
OVF
Figure 11.8 Setting of Overflow Flag (OVF)
285
11.4
Interrupts
Each channel in the 8-bit timer can generate three types of interrupts: compare-match A and B (CMIA and CMIB), and overflow (OVI). Each interrupt can be enabled or disabled by an enable bit in TCR. Independent signals are sent to the interrupt controller for each interrupt. Table 11.3 lists information about these interrupts. Table 11.3 8-Bit Timer Interrupts
Interrupt CMIA CMIB OVI Description Requested by CMFA Requested by CMFB Requested by OVF Low Priority High
11.5
Sample Application
In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle. The control bits are set as follows: 1. In TCR, CCLR1 is cleared to 0 and CCLR0 is set to 1 so that the timer counter is cleared when its value matches the constant in TCORA. 2. In TCSR, bits OS3 to OS0 are set to 0110, causing the output to change to 1 on compare-match A and to 0 on compare-match B. With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with a pulse width determined by TCORB. No software intervention is required.
TCNT H'FF TCORA TCORB H'00 Clear counter
TMO pin
Figure 11.9 Example of Pulse Output
286
11.6
Application Notes
Application programmers should note that the following types of contention can occur in the 8-bit timer. 11.6.1 Contention between TCNT Write and Clear
If an internal counter clear signal is generated during the T3 state of a write cycle to the timer counter, the clear signal takes priority and the write is not performed. Figure 11.10 shows this type of contention.
Write cycle: CPU writes to TCNT T1 T2 T3
o
Internal address bus Internal write signal
TCNT address
Counter clear signal
TCNT
N
H'00
Figure 11.10 TCNT Write-Clear Contention
287
11.6.2
Contention between TCNT Write and Increment
If a timer counter increment pulse is generated during the T3 state of a write cycle to the timer counter, the write takes priority and the timer counter is not incremented. Figure 11.11 shows this type of contention.
Write cycle: CPU writes to TCNT T1 T2 T3
o
Internal address bus
TCNT address
Internal write signal
TCNT clock pulse
TNCT
N
M Write data
Figure 11.11 TCNT Write-Increment Contention
288
11.6.3
Contention between TCOR Write and Compare-Match
If a compare-match occurs during the T3 state of a write cycle to TCORA or TCORB, the write takes priority and the compare-match signal is inhibited. Figure 11.12 shows this type of contention.
Write cycle: CPU writes to TCORA or TCORB T1 T2 T3
o
Internal address bus
TCOR address
Internal write signal
TCNT
N
N+1
TCORA or TCORB
N
M TCOR write data
Compare-match A or B signal Inhibited
Figure 11.12 Contention between TCOR Write and Compare-Match
289
11.6.4
Contention between Compare-Match A and Compare-Match B
If identical time constants are written in TCORA and TCORB, causing compare-match A and B to occur simultaneously, any conflict between the output selections for compare-match A and B is resolved by following the priority order in table 11.4. Table 11.4 Priority of Timer Output
Output Selection Toggle 1 output 0 output No change Low Priority High
11.6.5
Incrementation Caused by Changing of Internal Clock Source
When an internal clock source is changed, the changeover may cause the timer counter to increment. This depends on the time at which the clock select bits (CKS1, CKS0) are rewritten, as shown in table 11.5. The pulse that increments the timer counter is generated at the falling edge of the internal clock source signal. If clock sources are changed when the old source is high and the new source is low, as in case number 3 in table 11.5, the changeover generates a falling edge that triggers the TCNT clock pulse and increments the timer counter. Switching between an internal and external clock source can also cause the timer counter to increment.
290
Table 11.5 Effect of Changing Internal Clock Sources
No. 1 Description Low low* : Clock select bits are rewritten while both clock sources are low.
1
Timing
Old clock source New clock source TCNT clock pulse TCNT N CKS rewrite N+1
2
Low high* : Clock select bits are rewritten while old clock source is low and new clock source is high.
2
Old clock source New clock source TCNT clock pulse
TCNT
N
N+1
N+2 CKS rewrite
Notes: 1. Including a transition from low to the stopped state (CKS1 = 0, CKS0 = 0), or a transition from the stopped state to low. 2. Including a transition from the stopped state to high.
291
Table 11.5 Effect of Changing Internal Clock Sources (cont)
No. 3 Description High low* : Clock select bits are rewritten while old clock source is high and new clock source is low.
3
Timing
Old clock source
New clock source *4 TCNT clock pulse
TCNT
N
N+1 CKS rewrite
N+2
4
High high: Clock select bits are rewritten while both clock sources are high.
Old clock source
New clock source TCNT clock pulse
TCNT
N
N+1
N+2 CKS rewrite
Notes: 3. Including a transition from high to the stopped state. 4. The switching of clock sources is regarded as a falling edge that increments TCNT.
292
Section 12 Programmable Timing Pattern Controller
12.1 Overview
The H8/3318 has a built-in programmable timing pattern controller (TPC) that provides pulse outputs by using free-running timer 0 or 1 (FRT0 or FRT1) as a time base. The TPC pulse outputs are divided into 4-bit groups (group 3 to group 0) that can operate simultaneously and independently. 12.1.1 Features
The TPC has the following features: * 16-bit output data Maximum 16-bit data can be output. TPC output can be enabled on a bit-by-bit basis. * Four output groups Output trigger signals can be selected in 4-bit groups to provide up to four different 4-bit outputs. * Selectable output trigger signals Output trigger signals can be selected for each group from the compare-match signals of FRT0 and FRT1. * Non-overlap mode A non-overlap margin can be provided between pulse outputs. * Can operate together with the data transfer unit (DTU) The compare-match signals selected as trigger signals can activate the DTU for sequential output of data without CPU intervention.
293
12.1.2
Block Diagram
Figure 12.1 shows a block diagram of the TPC.
FRT0 and FRT1 compare-match signals
P1DDR Control logic NDER1 TPMR
P2DDR NDER2 TPCR Internal data bus
TP15 TP14 TP13 TP12 TP11 TP10 TP9 TP8 TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0
Pulse output pins, group 3 P2DR Pulse output pins, group 2 Pulse output pins, group 1 P1DR Pulse output pins, group 0 NDRA NDRB
Legend TPMR: TPCR: NDER2: NDER1: P2DDR: P1DDR: NDRB: NDRA: P2DR: P1DR:
TPC output mode register TPC output control register Next data enable register 2 Next data enable register 1 Port 2 data direction register Port 1 data direction register Next data register B Next data register A Port 2 data register Port 1 data register
Figure 12.1 TPC Block Diagram
294
12.1.3
TPC Pins
Table 12.1 summarizes the TPC output pins. Table 12.1 TPC Pins
Name TPC output 0 TPC output 1 TPC output 2 TPC output 3 TPC output 4 TPC output 5 TPC output 6 TPC output 7 TPC output 8 TPC output 9 TPC output 10 TPC output 11 TPC output 12 TPC output 13 TPC output 14 TPC output 15 Symbol TP 0 TP 1 TP 2 TP 3 TP 4 TP 5 TP 6 TP 7 TP 8 TP 9 TP 10 TP 11 TP 12 TP 13 TP 14 TP 15 I/O Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Group 3 pulse output Group 2 pulse output Group 1 pulse output Function Group 0 pulse output
295
12.1.4
Registers
Table 12.2 summarizes the TPC registers. Table 12.2 TPC Registers
Name Port 1 data direction register Port 1 data register Port 2 data direction register Port 2 data register TPC output mode register TPC output control register Next data enable register 2 Next data enable register 1 Next data register A Next data register B Abbreviation P1DDR P1DR P2DDR P2DR TPMR TPCR NDER2 NDER1 NDRA NDRB R/W W R/(W)* W R/(W)* R/W R/W R/W R/W R/W R/W
1 1
Initial Value H'00 H'00 H'00 H'00 H'F0 H'FF H'00 H'00 H'00 H'00
Address H'FFB0 H'FFB2 H'FFB1 H'FFB3 H'FFEA H'FFEB H'FFCD H'FFD5 H'FFCF/H'FFD7*2 H'FFCE/H'FFD6* 2
Notes: 1. Bits used for TPC output cannot be written to. 2. The NDRA address is H'FFCF when the same output trigger is selected for TPC output groups 0 and 1 by settings in TPCR. When the output triggers are different, the NDRA address is H'FFD7 for group 0 and H'FFA5 for group 1. Similarly, the address of NDRB is H'FFCE when the same output trigger is selected for TPC output groups 2 and 3 by settings in TPCR. When the output triggers are different, the NDRB address is H'FFD6 for group 2 and H'FFCE for group 3.
296
12.2
12.2.1
Register Descriptions
Port 1 Data Direction Register (P1DDR)
P1DDR is an 8-bit write-only register that selects input or output for each pin in port 1.
Bit 7 6 5 4 3 2 1 0
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
Port 1 is multiplexed with pins TP7 to TP0. Bits corresponding to pins used for TPC output must be set to 1. For further information about P1DDR, see section 8.2, Port 1. 12.2.2 Port 1 Data Register (P1DR)
P1DR is an 8-bit readable/writable register that stores TPC output data for groups 0 and 1, when these TPC output groups are used.
Bit 7 P17 Initial value Read/Write 0 R/(W)* 6 P16 0 R/(W)* 5 P15 0 R/(W)* 4 P14 0 R/(W)* 3 P13 0 R/(W)* 2 P12 0 R/(W)* 1 P11 0 R/(W)* 0 P10 0 R/(W)*
Note: * Bits selected for TPC output by NDER1 settings become read-only bits.
For further information about P1DR, see section 8.2, Port 1. 12.2.3 Port 2 Data Direction Register (P2DDR)
P2DDR is an 8-bit write-only register that selects input or output for each pin in port 2.
Bit 7 6 5 4 3 2 1 0
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
Port 2 is multiplexed with pins TP15 to TP8. Bits corresponding to pins used for TPC output must be set to 1. For further information about P2DDR, see section 8.3, Port 2.
297
12.2.4
Port 2 Data Register (P2DR)
P2DR is an 8-bit readable/writable register that stores TPC output data for groups 2 and 3, when these TPC output groups are used.
Bit 7 P27 Initial value Read/Write 0 R/(W)* 6 P26 0 R/(W)* 5 P25 0 R/(W)* 4 P24 0 R/(W)* 3 P23 0 R/(W)* 2 P22 0 R/(W)* 1 P21 0 R/(W)* 0 P20 0 R/(W)*
Note: * Bits selected for TPC output by NDER2 settings become read-only bits.
For further information about P2DR, see section 8.3, Port 2. 12.2.5 Next Data Register A (NDRA)
NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups 1 and 0 (pins TP7 to TP0). During TPC output, when an FRT0 or FRT1 compare-match event specified in TPCR occurs, NDRA contents are transferred to the corresponding bits in P1DR. The address of NDRA differs depending on whether TPC output groups 0 and 1 have the same output trigger or different output triggers. NDRA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Same Trigger for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by the same compare-match event, the NDRA address is H'FFCF. The upper 4 bits belong to group 1 and the lower 4 bits to group 0. Address H'FFD7 consists entirely of reserved bits that cannot be modified and always read 1. * Address H'FFCF
Bit 7 NDR7 Initial value Read/Write 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W
Bits 7 to 4--Next Data 7 to 4 (NDR7 to NDR4): These bits store the next output data for TPC output group 1. Bits 3 to 0--Next Data 3 to 0 (NDR3 to NDR0): These bits store the next output data for TPC output group 0.
298
* Address H'FFD7
Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
Bits 7 to 0--Reserved: These bits cannot be modified and are always read as 1. Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by different compare-match events, the address of the upper 4 bits of NDRA (group 1) is H'FFCF and the address of the lower 4 bits (group 0) is H'FFD7. Bits 3 to 0 of address H'FFCF and bits 7 to 4 of address H'FFD7 are reserved bits that cannot be modified and always read 1. * Address H'FFCF
Bit 7 NDR7 Initial value Read/Write 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
Bits 7 to 4--Next Data 7 to 4 (NDR7 to NDR4): These bits store the next output data for TPC output group 1. Bits 3 to 0--Reserved: These bits cannot be modified and are always read as 1. * Address H'FFD7
Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W
Bits 7 to 4--Reserved: These bits cannot be modified and are always read as 1. Bits 3 to 0--Next Data 3 to 0 (NDR3 to NDR0): These bits store the next output data for TPC output group 0.
299
12.2.6
Next Data Register B (NDRB)
NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups 3 and 2 (pins TP15 to TP8). During TPC output, when an FRT compare-match event specified in TPCR occurs, NDRB contents are transferred to the corresponding bits in P2DR. The address of NDRB differs depending on whether TPC output groups 2 and 3 have the same output trigger or different output triggers. NDRB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Same Trigger for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by the same compare-match event, the NDRB address is H'FFCE. The upper 4 bits belong to group 3 and the lower 4 bits to group 2. Address H'FFD6 consists entirely of reserved bits that cannot be modified and always read 1. * Address H'FFCE
Bit 7 NDR15 Initial value Read/Write 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W
Bits 7 to 4--Next Data 15 to 12 (NDR15 to NDR12): These bits store the next output data for TPC output group 3. Bits 3 to 0--Next Data 11 to 8 (NDR11 to NDR8): These bits store the next output data for TPC output group 2. * Address H'FFD6
Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
Bits 7 to 0--Reserved: These bits cannot be modified and are always read as 1.
300
Different Triggers for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by different compare-match events, the address of the upper 4 bits of NDRB (group 3) is H'FFCE and the address of the lower 4 bits (group 2) is H'FFD6. Bits 3 to 0 of address H'FFCE and bits 7 to 4 of address H'FFD6 are reserved bits that cannot be modified and always read 1. * Address H'FFCE
Bit 7 NDR15 Initial value Read/Write 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
Bits 7 to 4--Next Data 15 to 12 (NDR15 to NDR12): These bits store the next output data for TPC output group 3. Bits 3 to 0--Reserved: These bits cannot be modified and are always read as 1. * Address H'FFD6
Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W
Bits 7 to 4--Reserved: These bits cannot be modified and are always read as 1. Bits 3 to 0--Next Data 11 to 8 (NDR11 to NDR8): These bits store the next output data for TPC output group 2.
301
12.2.7
Next Data Enable Register 1 (NDER1)
NDER1 is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0 (TP7 to TP0) on a bit-by-bit basis.
Bit 7 NDER7 Initial value Read/Write 0 R/W 6 NDER6 0 R/W 5 NDER5 0 R/W 4 NDER4 0 R/W 3 NDER3 0 R/W 2 NDER2 0 R/W 1 NDER1 0 R/W 0 NDER0 0 R/W
If a bit is enabled for TPC output by NDER1, then when the FRT compare-match event selected in the TPC output control register (TPCR) occurs, the NDRA value is automatically transferred to the corresponding P1DR bit, updating the output value. If TPC output is disabled, the bit value is not transferred from NDRA to P1DR and the output value does not change. NDER1 is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0--Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or disable TPC output groups 1 and 0 (TP7 to TP0) on a bit-by-bit basis.
Bits 7 to 0: NDER7 to NDER0 0 1 Description TPC outputs TP7 to TP0 are disabled (NDR7 to NDR0 are not transferred to P17 to P1 0) (Initial value) TPC outputs TP7 to TP0 are enabled (NDR7 to NDR0 are transferred to P17 to P10)
302
12.2.8
Next Data Enable Register 2 (NDER2)
NDER2 is an 8-bit readable/writable register that enables or disables TPC output groups 3 and 2 (TP15 to TP8) on a bit-by-bit basis.
Bit 7 6 5 4 3 2 1 NDER9 0 R/W 0 NDER8 0 R/W
NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 Initial value Read/Write 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
If a bit is enabled for TPC output by NDER2, then when the FRT compare-match event selected in the TPC output control register (TPCR) occurs, the NDRB value is automatically transferred to the corresponding P2DR bit, updating the output value. If TPC output is disabled, the bit value is not transferred from NDRB to P2DR and the output value does not change. NDER2 is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0--Next Data Enable 15 to 8 (NDER15 to NDER8): These bits enable or disable TPC output groups 3 and 2 (TP15 to TP8) on a bit-by-bit basis.
Bits 7 to 0: NDER15 to NDER8 0 1 Description TPC outputs TP15 to TP8 are disabled (NDR15 to NDR8 are not transferred to P27 to P2 0) (Initial value) TPC outputs TP15 to TP8 are enabled (NDR15 to NDR8 are transferred to P27 to P2 0)
12.2.9
TPC Output Control Register (TPCR)
TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a group-by-group basis.
Bit 7 6 5 4 3 2 1 0
G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value Read/Write 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W
TPCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode.
303
Bits 7 and 6--Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits select the compare-match event that triggers TPC output group 3 (TP 15 to TP12).
Bit 7 G3CMS1 0 Bit 6 G3CMS0 0 1 1 0 1 Description TPC output group 3 (TP 15 to TP12 ) is triggered by compare-match A in FRT1 TPC output group 3 (TP 15 to TP12 ) is triggered by compare-match A in FRT0 TPC output group 3 (TP 15 to TP12 ) is triggered by compare-match B in FRT1 (compare-match A can be used for non-overlap operation) TPC output group 3 (TP 15 to TP12 ) is triggered by compare-match B in FRT0 (compare-match A can be used for non-overlap operation) (Initial value)
Bits 5 and 4--Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits select the compare-match event that triggers TPC output group 2 (TP 11 to TP8).
Bit 5 G2CMS1 0 Bit 4 G2CMS0 0 1 1 0 1 Description TPC output group 2 (TP 11 to TP8) is triggered by compare-match A in FRT1 TPC output group 2 (TP 11 to TP8) is triggered by compare-match A in FRT0 TPC output group 2 (TP 11 to TP8) is triggered by compare-match B in FRT1 (compare-match A can be used for non-overlap operation) TPC output group 2 (TP 11 to TP8) is triggered by compare-match B in FRT0 (compare-match A can be used for non-overlap operation) (Initial value)
304
Bits 3 and 2--Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits select the compare-match event that triggers TPC output group 1 (TP 7 to TP4).
Bit 3 G1CMS1 0 Bit 2 G1CMS0 0 1 1 0 1 Description TPC output group 1 (TP 7 to TP4) is triggered by compare-match A in FRT1 TPC output group 1 (TP 7 to TP4) is triggered by compare-match A in FRT0 TPC output group 1 (TP 7 to TP4) is triggered by compare-match B in FRT1 (compare-match A can be used for non-overlap operation) TPC output group 1 (TP 7 to TP4) is triggered by compare-match B in FRT0 (compare-match A can be used for non-overlap operation) (Initial value)
Bits 1 and 0--Group 0 Compare Match Select 1 and 0 (G0CMS1, G0CMS0): These bits select the compare-match event that triggers TPC output group 0 (TP 3 to TP0).
Bit 1 G0CMS1 0 Bit 0 G0CMS0 0 1 1 0 1 Description TPC output group 0 (TP 3 to TP0) is triggered by compare-match A in FRT1 TPC output group 0 (TP 3 to TP0) is triggered by compare-match A in FRT0 TPC output group 0 (TP 3 to TP0) is triggered by compare-match B in FRT1 (compare-match A can be used for non-overlap operation) TPC output group 0 (TP 3 to TP0) is triggered by compare-match B in FRT0 (compare-match A can be used for non-overlap operation) (Initial value)
305
12.2.10
TPC Output Mode Register (TPMR)
TPMR is an 8-bit readable/writable register that selects normal or non-overlapping TPC output for each group.
Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 G3NOV 0 R/W 2 G2NOV 0 R/W 1 G1NOV 0 R/W 0 G0NOV 0 R/W
The output trigger period of a non-overlapping TPC output waveform is set in output compare register A (OCRA) in the FRT0 or FRT1 channel selected for output triggering. The non-overlap margin is set in output compare register B (OCRB). The output values change at compare-match A and B. For details see section 12.3.4, Non-Overlapping TPC Output. TPMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 4--Reserved: These bits cannot be modified, and are always read as 1. Bit 3--Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping TPC output for group 3 (TP15 to TP12).
Bit 3 G3NOV 0 1 Description Normal TPC output in group 3 (output values change at the selected compare-match) Non-overlapping TPC output in group 3 (0 and 1 output at compare-match A and B, respectively) (Initial value)
Bit 2--Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping TPC output for group 2 (TP11 to TP8).
Bit 2 G2NOV 0 1 Description Normal TPC output in group 2 (output values change at the selected compare-match) Non-overlapping TPC output in group 2 (0 and 1 output at compare-match A and B, respectively) (Initial value)
306
Bit 1--Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping TPC output for group 1 (TP7 to TP4).
Bit 1 G1NOV 0 1 Description Normal TPC output in group 1 (output values change at the selected compare-match) Non-overlapping TPC output in group 1 (0 and 1 output at compare-match A and B, respectively) (Initial value)
Bit 0--Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping TPC output for group 0 (TP3 to TP0).
Bit 0 G0NOV 0 1 Description Normal TPC output in group 0 (output values change at the selected compare-match) Non-overlapping TPC output in group 0 (0 and 1 output at compare-match A and B, respectively) (Initial value)
307
12.3
12.3.1
Operation
Overview
When corresponding bits in P1DDR or P2DDR and NDER1 or NDER2 are set to 1, TPC output is enabled. The TPC output initially consists of the corresponding P1DR or P2DR contents. When a compare-match event selected in TPCR occurs, the corresponding NDRA or NDRB bit contents are transferred to P1DR or P2DR to update the output values. Figure 12.2 illustrates the TPC output operation. Table 12.3 summarizes the TPC operating conditions.
DDR Q
NDER Q Output trigger signal
C Q TPC output pin DR D Q NDR D Internal data bus
Figure 12.2 TPC Output Operation Table 12.3 TPC Operating Conditions
NDER 0 DDR 0 1 1 0 Pin Function General-purpose input port General-purpose output port General-purpose input port (but software cannot write to the DR bit, and when compare-match occurs, the NDR bit value is transferred to the DR bit) TPC pulse output
1
Sequential output of up to 16-bit patterns is possible by writing new output data to NDRA and NDRB before the next compare-match. For information on non-overlapping operation, see section 12.3.4, Non-Overlapping TPC Output.
308
12.3.2
Output Timing
If TPC output is enabled, NDRA/NDRB contents are transferred to P1DR/P2DR and output when the selected compare-match event occurs. Figure 12.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare-match A.
o
FRC
N
N+1
OCRA
N
Compare-match A signal
NDRB
n
P2DR
m
n
TP8 to TP15
m
n
Figure 12.3 Timing of Transfer of Next Data Register Contents and Output (Example)
309
12.3.3
Normal TPC Output
Sample Setup Procedure for Normal TPC Output: Figure 12.4 shows a sample procedure for setting up normal TPC output.
Normal TPC output
Select OCR functions
1
1. Set TCR or TOCR in the selected FRT channel to disable unwanted output signals. 2. Set the TPC output trigger period. 3. Select the counter clock source with bits CKS1 and CKS0 in TCR. Select the counter clear source with bit CCLRA in TCSR. 4. Enable the OCI interrupt in TIER or TCR. The DTU can also be set up to transfer data to the next data register. 5. Set the initial output values in the DR bits of the input/output port pins to be used for TPC output. 6. Set the DDR bits of the input/output port pins to be used for TPC output to 1. 7. Set the NDER bits of the pins to be used for TPC output to 1.
Set OCR value FRT setup Select counting operation
2
3
Select interrupt request
4
Set initial output data
5
Select port output
6
Port and TPC setup
Enable TPC output
7
Select TPC output trigger
8
8. Select the FRT compare-match event to be used as the TPC output trigger in TPCR. 9. Set the next TPC output values in the NDR bits. 10. At each OCI interrupt, set the next output values in the NDR bits.
Set next TPC output data
9
Compare-match? Yes Set next TPC output data
No
10
Note: Avoid allowing compare-match to occur while steps 4 to 9 are being carried out.
Figure 12.4 Setup Procedure for Normal TPC Output (Example)
310
Example of Normal TPC Output (Example of Five-Phase Pulse Output): Figure 12.5 shows an example in which the TPC is used for cyclic five-phase pulse output.
FRC value OCRA
FRC
Compare-match
H'0000 NDRB P2DR 80 00 CO 80 40 CO 60 40 20 60 30 20 10 30 18 10 08 18 88 08 80 88 CO 80
Time 40 CO
TP15 TP14 TP13 TP12 TP11
1. The FRT channel to be used as the output trigger channel is set up so that the counter will be cleared by compare-match A. The trigger period is set in OCRA. The OCIEA bit is set to 1 in TIER or TCR to enable the compare-match A interrupt. 2. H'F8 is written in P2DDR and NDER2, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set in TPCR to select compare-match in the FRT channel set up in step 1 as the output trigger. Output data H'80 is written in NDRB. 3. When compare-match A occurs, the NDRB contents are transferred to P2DR and output. The compare-match A (OCIA) interrupt service routine writes the next output data (H'C0) in NDRB. 4. Five-phase overlapping pulse output (one or two phases active at a time) can be obtained by writing H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88... at successive OCIA interrupts. If the DTU is set for activation by this interrupt, pulse output can be obtained without loading the CPU.
Figure 12.5 Normal TPC Output Example (Five-Phase Pulse Output)
311
12.3.4
Non-Overlapping TPC Output
Sample Setup Procedure for Non-Overlapping TPC Output: Figure 12.6 shows a sample procedure for setting up non-overlapping TPC output.
Non-overlapping TPC output 1. Set TCR or TOCR in the selected FRT channel to disable unwanted output signals. 2. Set the TPC output trigger period in OCRA and the non-overlap margin in OCRB. 3. Select the counter clock source with bits CKS1 and CKS0 in TCR. Select the counter clear source with bit CCLRA in TCSR. 4. Enable the OCIB interrupt in TIER or TCR. The DTU can also be set up to transfer data to the next data register. 5. Set the initial output values in the DR bits of the input/output port pins to be used for TPC output. 6. Set the DDR bits of the input/output port pins to be used for TPC output to 1. 7. Set the NDER bits of the pins to be used for TPC output to 1. 8. In TPCR, select the FRT compare-match event to be used as the TPC output trigger. 9. In TPMR, select the groups that will operate in non-overlap mode. 10. Set the next TPC output values in the NDR bits. 11. At each OCIB interrupt, write the next output value in the NDR bits.
Select OCR functions
1
Set OCR values FRT setup Select counting operation
2
3
Select interrupt requests
4
Set initial output data
5
Select TPC output
6
Enable TPC transfer Port and TPC setup Select TPC transfer trigger
7
8
Select non-overlapping groups
9
Set next TPC output data
10
Compare-match B? Yes Set next TPC output data
No
11
Note: Avoid allowing compare-match to occur while steps 4 to 10 are being carried out.
Figure 12.6 Setup Procedure for Non-Overlapping TPC Output (Example)
312
Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary NonOverlapping Output): Figure 12.7 shows an example of the use of TPC output for four-phase complementary non-overlapping pulse output.
FRC value OCRA OCRB H'0000 NDRB P2DR 95 00 95 65 05 65 59 41 59 56 50 56 95 14 95 65 05 65 Time FRC
Non-overlap margin TP15 TP14 TP13 TP12 TP11 TP10 TP9 TP8 1. The FRT channel to be used as the output trigger channel is set up so that the counter will be cleared by compare-match A. The trigger period is set in OCRA. The non-overlap margin is set in OCRB. The OCIEB bit is set to 1 in TIER or TCR to enable OCIB interrupts. 2. H'FF is written in P2DDR and NDER2, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set in TPCR to select compare-match in the FRT channel set up in step 1 as the output trigger. Bits G3NOV and G2NOV are set to 1 in TPMR to select non-overlapping output. Output data H'95 is written in NDRB. 3. After FRT operation begins, when compare-match A occurs, outputs change from 1 to 0. When compare-match B occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value of OCRB). The OCIB interrupt service routine writes the next output data (H'65) in NDRB. 4. Four-phase complementary non-overlapping pulse output can be obtained by writing H'59, H'56, H'95... at successive OCIB interrupts. If the DTU is set for activation by this interrupt, pulse output can be obtained without loading the CPU.
Figure 12.7 Non-Overlapping TPC Output Example (Four-Phase Complementary Non-Overlapping Pulse Output)
313
12.4
12.4.1
Application Notes
Operation of TPC Output Pins
TP 0 to TP15 are multiplexed with address output in the expanded modes. When address output is enabled in mode 1, the corresponding pins cannot be used for TPC output. The data transfer from NDR bits to DR bits takes place, however, regardless of the usage of the pin. Pin functions should be changed only under conditions in which the output trigger event will not occur. 12.4.2 Note on Non-Overlapping Output
During non-overlapping operation, the transfer of NDR bit values to DR bits takes place as follows. 1. NDR bits are always transferred to DR bits at compare-match B. 2. At compare-match A, NDR bits are transferred only if their value is 0. Bits are not transferred if their value is 1. Figure 12.8 illustrates the non-overlapping TPC output operation.
DDR Q
NDER Q Compare-match B Compare-match A
C Q TPC output pin DR D Q NDR D
Figure 12.8 Non-Overlapping TPC Output
314
Therefore, 0 data can be transferred ahead of 1 data by making compare-match A occur before compare-match B. NDR contents should not be altered during the interval from compare-match A to compare-match B (the non-overlap margin). This can be accomplished by having the OCIB interrupt service routine write the next data in NDR, or by having the OCIB interrupt activate the DTU. The next data must be written before the next compare-match A occurs. Figure 12.9 shows the timing relationships.
Comparematch B Comparematch A
NDR write
NDR write
NDR
DR 0 output 0/1 output 0 output 0/1 output
Do not write to NDR in this interval
Write to NDR in this interval
Do not write to NDR in this interval
Write to NDR in this interval
Figure 12.9 Non-Overlapping Operation and NDR Write Timing
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Section 13 Watchdog Timer
13.1 Overview
The H8/3318 on-chip watchdog timer (WDT) module can monitor system operation by requesting a nonmaskable interrupt internally if a system crash allows the timer count to overflow. It can also generate an internal chip reset instead of a nonmaskable interrupt. When this watchdog function is not needed, the WDT module can be used as an interval timer. In interval timer mode, it requests an OVF interrupt at each counter overflow. 13.1.1 Features
* Selection of eight clock sources * Selection of two modes: Watchdog timer mode Interval timer mode * Counter overflow generates an interrupt request or reset: Reset or NMI request in watchdog timer mode OVF interrupt request in interval timer mode
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13.1.2
Block Diagram
Figure 13.1 is a block diagram of the watchdog timer.
Reset or internal NMI (Watchdog timer mode) Interrupt signals OVF (Interval timer mode) Interrupt control Overflow Internal data bus Read/write control TCSR Internal clock source Clock Clock select Legend TCNT: Timer counter TCSR: Timer control/status register oP/2 oP/32 oP/64 oP/128 oP/256 oP/512 oP/2048 oP/4096
TCNT
Figure 13.1 Block Diagram of Watchdog Timer 13.1.3 Register Configuration
Table 13.1 lists information on the watchdog timer registers. Table 13.1 Register Configuration
Initial Value H'00 H'10 Addresses Write H'FFAA (word transfer) H'FFAA (word transfer) Read H'FFAB H'FFAA
Name Timer counter Timer control/status register
Abbreviation TCNT TCSR
R/W R/W R/(W)*
Note: * Software can write a 0 to clear the status flag bits, but cannot write 1.
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13.2
13.2.1
Bit
Register Descriptions
Timer Counter (TCNT)
7 6 5 4 3 2 1 0
Initial value Read/Write
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
The watchdog timer counter (TCNT) is a read/write 8-bit up-counter. (TCNT is write-protected by a password. See section 13.2.3, Register Access, for details.) When the timer enable bit (TME) in the timer control/status register (TCSR) is set to 1, the timer counter starts counting pulses of an internal clock source selected by clock select bits 2 to 0 (CKS2 to CKS0) in TCSR. When the count overflows (changes from H'FF to H'00), an overflow flag (OVF) in TCSR is set to 1. The watchdog timer counter is initialized to H'00 by a reset and when the TME bit is cleared to 0. Note: TCNT is more difficult to write to than other registers. See section 13.2.3, Register Access, for details. 13.2.2
Bit
Timer Control/Status Register (TCSR)
7 OVF 6 WT/IT 0 R/W 5 TME 0 R/W 4 -- 1 -- 3 RST/NMI 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
Initial value Read/Write
0 R/(W)*
Note: * Software can write a 0 in bit 7 to clear the flag, but cannot write a 1 in this bit.
The watchdog timer control/status register (TCSR) is an 8-bit read/write register that selects the timer mode and clock source and performs other functions. (TCSR is write-protected by a password. See section 13.2.3, Register Access, for details.) Bits 7 to 5 and bit 3 are initialized to 0 by a reset and in the standby modes. Bits 2 to 0 are initialized to 0 by a reset, but retain their values in the standby modes. Note: TCSR is more difficult to write to than other registers. See section 13.2.3, Register Access, for details.
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Bit 7--Overflow Flag (OVF): Indicates that the watchdog timer count has overflowed.
Bit 7 OVF 0 1 Description To clear OVF, the CPU must read OVF after it has been set to 1, then write a 0 in this bit (Initial value) Set to 1 when TCNT changes from H'FF to H'00
Bit 6--Timer Mode Select (WT/IT): Selects whether to operate in watchdog timer mode or interval timer mode.
Bit 6 WT/IT 0 1 Description Interval timer mode (OVF request) Watchdog timer mode (reset or NMI request) (Initial value)
Bit 5--Timer Enable (TME): Enables or disables the timer.
Bit 5 TME 0 1 Description TCNT is initialized to H'00 and stopped TCNT runs and requests a reset or an interrupt when it overflows (Initial value)
Bit 4--Reserved: This bit cannot be modified and is always read as 1. Bit 3--Reset or NMI Select (RST/NMI): Selects either an internal reset or the NMI function at watchdog timer overflow.
Bit 3 RST/NMI 0 1 Description NMI function enabled Reset function enabled (Initial value)
Bits 2-0--Clock Select (CKS2-CKS0): These bits select one of eight clock sources obtained by dividing the system clock (o). The overflow interval listed in the following table is the time from when the watchdog timer counter begins counting from H'00 until an overflow occurs. In interval timer mode, OVF interrupts are requested at this interval.
320
Bit 2 CKS2 0
Bit 1 CKS1 0
Bit 0 CKS0 0 1
Clock Source oP/2 oP/32 oP/64 oP/128 oP/256 oP/512 oP/2048 oP/4096
Overflow Interval (oP = 10 MHz) 51.2 s 819.2 s 1.6 ms 3.3 ms 6.6 ms 13.1 ms 52.4 ms 104.9 ms (Initial value)
1
0 1
1
0
0 1
1
0 1
13.2.3
Register Access
The watchdog timer's TCNT and TCSR registers are more difficult to write to than other registers. The procedures for writing and reading these registers are given below. Writing to TCNT and TCSR: Word access is required. Byte data transfer instructions cannot be used for write access. The TCNT and TCSR registers have the same write address. The write data must be contained in the lower byte of a word written at this address. The upper byte must contain H'5A (password for TCNT) or H'A5 (password for TCSR). See figure 13.2. The result of the access depicted in figure 13.2 is to transfer the write data from the lower byte to TCNT or TCSR.
Writing to TCNT H'FFAA 15 H'5A 87 Write data 0
Writing to TCSR H'FFAA
15 H'A5
87 Write data
0
Figure 13.2 Writing to TCNT and TCSR Reading TCNT and TCSR: The read addresses are H'FFAA for TCSR and H'FFAB for TCNT, as indicated in table 13.2. These two registers are read like other registers. Byte access instructions can be used.
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Table 13.2 Read Addresses of TCNT and TCSR
Read Address H'FFAA H'FFAB Register TCSR TCNT
13.3
13.3.1
Operation
Watchdog Timer Mode
The watchdog timer function begins operating when software sets the WT/IT and TME bits to 1 in TCSR. Thereafter, software should periodically rewrite the contents of the timer counter (normally by writing H'00) to prevent the count from overflowing. If a program crash allows the timer count to overflow, the watchdog timer either requests a nonmaskable interrupt (NMI) or resets the entire chip for 518 system clocks (o), depending on the status of bit 3 of TCSR. Figure 13.3 shows the operation. NMI requests from the watchdog timer have the same vector as NMI requests from the NMI pin. NMI requests from the watchdog timer and pin NMI should not be handled simultaneously. A reset from the watchdog timer has the same vector as an external reset from the RES pin. The reset source can be determined by the XRST bit in SYSCR.
Watchdog timer overflow H'FF
TCNT count
WT/IT = 1 TME = 1
H'00 OVF = 1 WT/IT = 1 TME = 1 H'00 written to TCNT H'00 written to TCNT
Time t
Reset generated 518 o
Figure 13.3 Operation in Watchdog Timer Mode
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13.3.2
Interval Timer Mode
Interval timer operation begins when the WT/IT bit is cleared to 0 and the TME bit is set to 1. In interval timer mode, an OVF request is generated each time the timer count overflows. This function can be used to generate OVF requests at regular intervals. See figure 13.4.
H'FF
TCNT count
Time t
H'00
WT/IT = 0 TME = 1
OVF request
OVF request
OVF request
OVF request
OVF request
Figure 13.4 Operation in Interval Timer Mode 13.3.3 Setting the Overflow Flag
The OVF bit is set to 1 when the timer count overflows. Simultaneously, the WDT module requests an internal reset, NMI, or OVF interrupt. The timing is shown in figure 13.5.
o
TCNT Internal overflow signal
H'FF
H'00
OVF
Figure 13.5 Setting the OVF Bit
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13.4
13.4.1
Application Notes
Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T3 state of a write cycle to the timer counter, the write takes priority and the timer counter is not incremented. See figure 13.6.
Write cycle (CPU writes to TCNT) T1 o T2 T3
Internal address bus
TCNT address
Internal write signal
TCNT clock pulse
TCNT
N
M
Counter write data
Figure 13.6 TCNT Write-Increment Contention 13.4.2 Changing the Clock Select Bits (CKS2 to CKS0)
Software should stop the watchdog timer (by clearing the TME bit to 0) before changing the value of the clock select bits. If the clock select bits are modified while the watchdog timer is running, the timer count may be incremented incorrectly. 13.4.3 Recovery from Software Standby Mode
TCSR bits, except bits 0-2, and the TCNT counter are reset when the chip recovers from software standby mode. Re-initialize the watchdog timer as necessary to resume normal operation.
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Section 14 Serial Communication Interface
14.1 Overview
The H8/3318 includes two serial communication interface channels (SCI0 and SCI1) for transferring serial data to and from other chips. Either synchronous or asynchronous communication can be selected. 14.1.1 Features
The features of the on-chip serial communication interface are: * Asynchronous mode An H8/3318 microcontroller can communicate with a UART (Universal Asynchronous Receiver/Transmitter), ACIA (Asynchronous Communication Interface Adapter), or other chip that employs standard asynchronous serial communication. It also has a multiprocessor communication function for communication with other processors. Twelve data formats are available. Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Multiprocessor bit: 1 or 0 Error detection: Parity, overrun, and framing errors Break detection: When a framing error occurs, the break condition can be detected by reading the level of the RxD line directly. Synchronous mode The SCI can communicate with chips able to perform clocked synchronous data transfer. Data length: 8 bits Error detection: Overrun errors Full duplex communication The transmitting and receiving sections are independent, so each channel can transmit and receive simultaneously. Both the transmit and receive sections use double buffering, so continuous data transfer is possible in either direction. Built-in baud rate generator Any specified bit rate can be generated. Internal or external clock source The SCI can operate on an internal clock signal from the baud rate generator, or an external clock signal input at the SCK0 or SCK1 pin.
*
*
* *
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* Four interrupts TDR-empty, TSR-empty, receive-end, and receive-error interrupts are requested independently. 14.1.2 Block Diagram
Figure 14.1 shows a block diagram of one serial communication interface channel.
Bus interface BRR Baud rate generator Clock
Internal data bus
Module data bus
RDR
TDR
SSR SCR SMR
RxD
RSR
TSR
SCMR Communication control
TxD
Parity generate Parity check
Internal o oP/4 clock oP/16 oP/64
SCK
External clock source TEI TXI RXI ERI Interrupt signals
Legend RSR: Receive shift register (8 bits) RDR: Receive data register (8 bits) TSR: Transmit shift register (8 bits) TDR: Transmit data register (8 bits) SMR: Serial mode register (8 bits) SCR: Serial control register (8 bits) SSR: Serial status register (8 bits) BRR: Bit rate register (8 bits) SCMR: Serial communication mode register (8 bits)
Figure 14.1 Block Diagram of Serial Communication Interface
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14.1.3
Input and Output Pins
Table 14.1 lists the input and output pins used by the SCI module. Table 14.1 SCI Input/Output Pins
Channel 0 Name Serial clock Receive data Transmit data 1 Serial clock Receive data Transmit data Abbr.* SCK 0 RxD0 TxD0 SCK 1 RxD1 TxD1 I/O Input/output Input Output Input/output Input Output Function Serial clock input and output Receive data input Transmit data output Serial clock input and output Receive data input Transmit data output
Note: * In this manual, the channel subscripts are normally omitted.
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14.1.4
Register Configuration
Table 14.2 lists the SCI registers. These registers specify the operating mode (synchronous or asynchronous), data format and bit rate, and control the transmit and receive sections. Table 14.2 SCI Registers
Channel 0 Name Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register Serial communication mode register 1 Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register 0 and 1 Abbr. RSR RDR TSR TDR SMR SCR SSR BRR SCMR RSR RDR TSR TDR SMR SCR SSR BRR R/W -- R -- R/W R/W R/W R/(W)* R/W R/W -- R -- R/W R/W R/W R/(W)* R/W R/W Value -- H'00 -- H'FF H'00 H'00 H'84 H'FF H'F2 -- H'00 -- H'FF H'00 H'00 H'84 H'FF H'1C Address -- H'FFDD -- H'FFDB H'FFD8 H'FFDA H'FFDC H'FFD9 H'FFDE -- H'FF8D -- H'FF8B H'FF88 H'FF8A H'FF8C H'FF89 H'FFC3
Serial/timer control register STCR
Note: * Software can write a 0 to clear the flags in bits 7 to 3, but cannot write 1 in these bits.
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14.2
14.2.1
Bit
Register Descriptions
Receive Shift Register (RSR)
7 6 5 4 3 2 1 0
Read/Write
--
--
--
--
--
--
--
--
RSR is a shift register that converts incoming serial data to parallel data. When one data character has been received, it is transferred to the receive data register (RDR). The CPU cannot read or write RSR directly. 14.2.2
Bit
Receive Data Register (RDR)
7 6 5 4 3 2 1 0
Initial value Read/Write
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
RDR stores received data. As each character is received, it is transferred from RSR to RDR, enabling RSR to receive the next character. This double-buffering allows the SCI to receive data continuously. RDR is a read-only register. RDR is initialized to H'00 by a reset and in the standby modes. 14.2.3
Bit
Transmit Shift Register (TSR)
7 6 5 4 3 2 1 0
Read/Write
--
--
--
--
--
--
--
--
TSR is a shift register that converts parallel data to serial transmit data. When transmission of one character is completed, the next character is moved from the transmit data register (TDR) to TSR and transmission of that character begins. If the TDRE bit is still set to 1, however, nothing is transferred to TSR. The CPU cannot read or write TSR directly.
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14.2.4
Bit
Transmit Data Register (TDR)
7 6 5 4 3 2 1 0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
TDR is an 8-bit readable/writable register that holds the next data to be transmitted. When TSR becomes empty, the data written in TDR is transferred to TSR. Continuous data transmission is possible by writing the next data in TDR while the current data is being transmitted from TSR. TDR is initialized to H'FF by a reset and in the standby modes. 14.2.5
Bit
Serial Mode Register (SMR)
7 C/A 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
Initial value Read/Write
0 R/W
SMR is an 8-bit readable/writable register that controls the communication format and selects the clock source of the on-chip baud rate generator. It is initialized to H'00 by a reset and in the standby modes. For further information on the SMR settings and communication formats, see tables 14.5 and 14.7 in section 14.3, Operation. Bit 7--Communication Mode (C/A): This bit selects asynchronous or synchronous communication mode.
Bit 7 C/A 0 1 Description Asynchronous communication Synchronous communication (Initial value)
Bit 6--Character Length (CHR): This bit selects the character length in asynchronous mode. It is ignored in synchronous mode.
Bit 6 CHR 0 1 Description 8 bits per character (Initial value)
7 bits per character (Bits 0 to 6 of TDR and RDR are used for transmitting and receiving, respectively)
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Bit 5--Parity Enable (PE): This bit selects whether to add a parity bit in asynchronous mode. It is ignored in synchronous mode, and when a multiprocessor format is used.
Bit 5 PE 0 Description Transmit: No parity bit is added. Receive: Parity is not checked. 1 Transmit: A parity bit is added. Receive: Parity is checked. (Initial value)
Bit 4--Parity Mode (O/E ): In asynchronous mode, when parity is enabled (PE = 1), this bit selects even or odd parity. Even parity means that a parity bit is added to the data bits for each character to make the total number of 1's even. Odd parity means that the total number of 1's is made odd. This bit is ignored when PE = 0, or when a multiprocessor format is used. It is also ignored in synchronous mode.
Bit 4 O/E 0 1 Description Even parity Odd parity (Initial value)
Bit 3--Stop Bit Length (STOP): This bit selects the number of stop bits. It is ignored in synchronous mode.
Bit 3 STOP 0 Description One stop bit Transmit: One stop bit is added. Receive: One stop bit is checked to detect framing errors. 1 Two stop bits Transmit: Two stop bits are added. Receive: The first stop bit is checked to detect framing errors. If the second stop bit is a space (0), it is regarded as the next start bit. (Initial value)
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Bit 2--Multiprocessor Mode (MP): This bit selects the multiprocessor format. When multiprocessor format is selected, the parity settings of the parity enable bit (PE) and parity mode bit (O/E) are ignored. The MP bit setting is valid only in asynchronous communication, and is ignored in synchronous communication.
Bit 2 MP 0 1 Description Multiprocessor communication function is disabled. Multiprocessor communication function is enabled. (Initial value)
Bits 1 and 0--Clock Select 1 and 0 (CKS1 and CKS0): These bits select the clock source of the on-chip baud rate generator.
Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 Description o clock oP/4 clock oP/16 clock oP/64 clock (Initial value)
14.2.6
Bit
Serial Control Register (SCR)
7 TIE 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W
Initial value Read/Write
0 R/W
SCR is an 8-bit readable/writable register that enables or disables various SCI functions. It is initialized to H'00 by a reset and in the standby modes. Bit 7--Transmit Interrupt Enable (TIE): This bit enables or disables the TDR-empty interrupt (TXI) requested when the transmit data register empty (TDRE) bit in the serial status register (SSR) is set to 1.
Bit 7 TIE 0 1 Description The TDR-empty interrupt request (TXI) is disabled. The TDR-empty interrupt request (TXI) is enabled. (Initial value)
332
Bit 6--Receive Interrupt Enable (RIE): This bit enables or disables the receive-end interrupt (RXI) requested when the receive data register full (RDRF) bit in the serial status register (SSR) is set to 1, and the receive error interrupt (ERI) requested when the overrun error (ORER), framing error (FER), or parity error (PER) bit in the serial status register (SSR) is set to 1.
Bit 6 RIE 0 1 Description The receive-end interrupt (RXI) and receive-error (ERI) requests are disabled. (Initial value) The receive-end interrupt (RXI) and receive-error (ERI) requests are enabled.
Bit 5--Transmit Enable (TE): This bit enables or disables the transmit function. When the transmit function is enabled, the TxD pin is automatically used for output. When the transmit function is disabled, the TxD pin can be used as a general-purpose I/O port.
Bit 5 TE 0 Description The transmit function is disabled. The TxD pin can be used for general-purpose I/O. 1 The transmit function is enabled. The TxD pin is used for output. (Initial value)
Bit 4--Receive Enable (RE): This bit enables or disables the receive function. When the receive function is enabled, the RxD pin is automatically used for input. When the receive function is disabled, the RxD pin is available as a general-purpose I/O port.
Bit 4 RE 0 Description The receive function is disabled. The RxD pin can be used for general-purpose I/O. 1 The receive function is enabled. The RxD pin is used for input. (Initial value)
Bit 3--Multiprocessor Interrupt Enable (MPIE): When serial data is received in a multiprocessor format, this bit enables or disables the receive-end interrupt (RXI) and receiveerror interrupt (ERI) until data with the multiprocessor bit set to 1 is received. It also enables or disables the transfer of received data from RSR to RDR, and enables or disables setting of the RDRF, FER, PER, and ORER bits in the serial status register (SSR). The MPIE bit is ignored when the MP bit is cleared to 0, and in synchronous mode. Clearing the MPIE bit to 0 disables the multiprocessor receive interrupt function. In this condition data is received regardless of the value of the multiprocessor bit in the receive data.
333
Setting the MPIE bit to 1 enables the multiprocessor receive interrupt function. In this condition, if the multiprocessor bit in the receive data is 0, the receive-end interrupt (RXI) and receive-error interrupt (ERI) are disabled, the receive data is not transferred from RSR to RDR, and the RDRF, FER, PER, and ORER bits in the serial status register (SSR) are not set. If the multiprocessor bit is 1, however, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0, the receive data is transferred from RSR to RDR, the FER, PER, and ORER bits can be set, and the receive-end and receive-error interrupts are enabled.
Bit 3 MPIE 0 1 Description The multiprocessor receive interrupt function is disabled. (Normal receive operation) (Initial value)
The multiprocessor receive interrupt function is enabled. During the interval before data with the multiprocessor bit set to 1 is received, the receive interrupt request (RXI) and receive-error interrupt request (ERI) are disabled, the RDRF, FER, PER, and ORER bits are not set in the serial status register (SSR), and no data is transferred from the RSR to the RDR. The MPIE bit is cleared at the following times: 1. When 0 is written in MPIE 2. When data with the multiprocessor bit set to 1 is received
Bit 2--Transmit-End Interrupt Enable (TEIE): This bit enables or disables the TSR-empty interrupt (TEI) requested when the transmit-end bit (TEND) in the serial status register (SSR) is set to 1.
Bit 2 TEIE 0 1 Description The TSR-empty interrupt request (TEI) is disabled. The TSR-empty interrupt request (TEI) is enabled. (Initial value)
Bit 1--Clock Enable 1 (CKE1): This bit selects the internal or external clock source for the baud rate generator. When the external clock source is selected, the SCK pin is automatically used for input of the external clock signal.
Bit 1 CKE1 0 Description Internal clock source When C/A = 1, the serial clock signal is output at the SCK pin. When C/A = 0, output depends on the CKE0 bit. 1 External clock source The SCK pin is used for input. (Initial value)
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Bit 0--Clock Enable 0 (CKE0): When an internal clock source is used in asynchronous mode, this bit enables or disables serial clock output at the SCK pin. This bit is ignored when the external clock is selected, or when synchronous mode is selected. For further information on the communication format and clock source selection, see table 14.6 in section 14.3, Operation.
Bit 0 CKE0 0 1 Description The SCK pin is not used by the SCI (and is available as a general-purpose I/O port). (Initial value) The SCK pin is used for serial clock output.
14.2.7
Bit
Serial Status Register (SSR)
7 TDRE 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W
Initial value Read/Write
1 R/(W)*
Note: * Software can write a 0 to clear the flags, but cannot write a 1 in these bits.
SSR is an 8-bit register that indicates transmit and receive status. It is initialized to H'84 by a reset and in the standby modes. Bit 7--Transmit Data Register Empty (TDRE): This bit indicates when transmit data can safely be written in TDR.
Bit 7 TDRE 0 Description To clear TDRE, the CPU must read TDRE after it has been set to 1, then write a 0 in this bit. Otherwise, when a data is written to TDR in the DTU bus cycle. 1 This bit is set to 1 at the following times: 1. When TDR contents are transferred to TSR 2. When the TE bit in SCR is cleared to 0 (Initial value)
335
Bit 6--Receive Data Register Full (RDRF): This bit indicates when one character has been received and transferred to RDR.
Bit 6 RDRF 0 Description To clear RDRF, the CPU must read RDRF after it has been set to 1, then write a 0 in this bit. (Initial value) Otherwise, when RDR is read in the DTU bus cycle. 1 This bit is set to 1 when one character is received without error and transferred from RSR to RDR.
Bit 5--Overrun Error (ORER): This bit indicates an overrun error during reception.
Bit 5 ORER 0 1 Description To clear ORER, the CPU must read ORER after it has been set to 1, then write a 0 in this bit. (Initial value) This bit is set to 1 if reception of the next character ends while the receive data register is still full (RDRF = 1).
Bit 4--Framing Error (FER): This bit indicates a framing error during data reception in asynchronous mode. It has no meaning in synchronous mode.
Bit 4 FER 0 1 Description To clear FER, the CPU must read FER after it has been set to 1, then write a 0 in this bit. (Initial value) This bit is set to 1 if a framing error occurs (stop bit = 0).
Bit 3--Parity Error (PER): This bit indicates a parity error during data reception in the asynchronous mode, when a communication format with parity bits is used. This bit has no meaning in the synchronous mode, or when a communication format without parity bits is used.
Bit 3 PER 0 1 Description To clear PER, the CPU must read PER after it has been set to 1, then write a 0 in this bit. (Initial value) This bit is set to 1 when a parity error occurs (the parity of the received data does not match the parity selected by the O/E bit in SMR).
336
Bit 2--Transmit End (TEND): This bit indicates that the serial communication interface has stopped transmitting because there was no valid data in TDR when the last bit of the current character was transmitted. The TEND bit is also set to 1 when the TE bit in the serial control register (SCR) is cleared to 0. The TEND bit is a read-only bit and cannot be modified directly. To use the TEI interrupt, first start transmitting data, which clears TEND to 0, then set TEIE to 1.
Bit 2 TEND 0 1 Description To clear TEND, the CPU must read TDRE after TDRE has been set to 1, then write a 0 in TDRE. (Initial value) This bit is set to 1 when: 1. TE = 0 2. TDRE = 1 at the end of transmission of a character
Bit 1--Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in data received in a multiprocessor format in asynchronous communication mode. This bit retains its previous value in synchronous mode, when a multiprocessor format is not used, or when the RE bit is cleared to 0 even if a multiprocessor format is used. MPB can be read but not written.
Bit 1 MPB 0 1 Description Multiprocessor bit = 0 in receive data. Multiprocessor bit = 1 in receive data. (Initial value)
Bit 0--Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit inserted in transmit data when a multiprocessor format is used in asynchronous communication mode. The MPBT bit is double-buffered in the same way as TSR and TDR. The MPBT bit has no effect in synchronous mode, or when a multiprocessor format is not used.
Bit 0 MPBT 0 1 Description Multiprocessor bit = 0 in transmit data. Multiprocessor bit = 1 in transmit data. (Initial value)
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14.2.8
Bit
Bit Rate Register (BRR)
7 6 5 4 3 2 1 0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in SMR, determines the bit rate output by the baud rate generator. BRR is initialized to H'FF by a reset and in the standby modes. Tables 14.3 to 14.6 show examples of BRR settings. Table 14.3 Examples of BRR Settings in Asynchronous Mode (When oP = o)
o (MHz) 2 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 0 0 0 0 0 -- -- 0 -- N 141 103 207 103 51 25 12 -- -- 1 -- Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 -- -- 0 -- n 1 1 0 0 0 0 0 0 0 -- 0 2.4576 N 174 127 255 127 63 31 15 7 3 -- 1 Error (%) -0.26 0 0 0 0 0 0 0 0 -- 0 n 1 1 1 0 0 0 0 0 0 0 -- N 212 155 77 155 77 38 19 9 4 2 -- 3 Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 -2.34 -2.34 -2.34 0 -- n 2 1 1 0 0 0 0 0 0 -- 0 3.6864 N 64 191 95 191 95 47 23 11 5 -- 2 Error (%) +0.70 0 0 0 0 0 0 0 0 -- 0
Note: If possible, the error should be within 1%.
338
Table 14.3 Examples of BRR Settings in Asynchronous Mode (When oP = o) (cont)
o (MHz) 4 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 1 1 0 0 0 0 0 -- 0 -- N 70 207 103 207 103 51 25 12 -- 3 -- Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 -- 0 -- n 2 1 1 0 0 0 0 0 0 0 0 4.9152 N 86 255 127 255 127 63 31 15 7 4 3 Error (%) +0.31 0 0 0 0 0 0 0 0 -1.70 0 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 5 Error (%) -0.25 +0.16 +0.16 +0.16 +0.16 +0.16 -1.36 +1.73 +1.73 0 +1.73 n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 6 Error (%) -0.44 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 -2.34 -2.34 0 -2.34
o (MHz) 6.144 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 108 79 159 79 159 79 39 19 4 5 4 Error (%) +0.08 0 0 0 0 0 0 0 0 +2.40 0 n 2 2 1 1 0 0 0 0 0 -- 0 7.3728 N 130 95 191 95 191 95 47 23 11 -- 5 Error (%) -0.07 0 0 0 0 0 0 0 0 -- 0 n 2 2 1 1 0 0 0 0 0 0 -- N 141 103 207 103 207 103 51 25 12 7 -- 8 Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 0 -- n 2 2 1 1 0 0 0 0 0 0 0 9.8304 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) -0.26 0 0 0 0 0 0 0 0 -1.70 0
Note: If possible, the error should be within 1%.
339
Table 14.3 Examples of BRR Settings in Asynchronous Mode (When oP = o) (cont)
o (MHz) 10 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 Error (%) -0.25 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 -1.36 +1.73 0 +1.73 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 -2.34 0 -2.34 n 2 2 2 1 1 0 0 0 0 0 0 12.288 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) +0.08 0 0 0 0 0 0 0 0 +2.4 0 n 3 2 2 1 1 0 0 0 0 0 0 14.7456 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) +0.70 0 0 0 0 0 0 0 0 -1.7 0
o (MHz) 16 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 0 +0.16
Note: If possible, the error should be within 1%.
340
Table 14.4 Examples of BRR Settings in Asynchronous Mode (When oP = o/2)
o (MHz) 2 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 0 0 0 0 -- -- -- 0 -- N 70 51 103 51 25 12 -- -- -- 0 -- Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 -- -- -- 0 -- n 1 1 0 0 0 0 0 0 0 -- 0 2.4576 N 86 63 255 127 63 31 15 7 3 -- 1 Error (%) 0.31 0 0 0 0 0 0 0 0 -- 0 n 1 1 1 0 0 0 0 0 -- -- -- N 106 77 38 77 38 19 9 4 -- -- -- 3 Error (%) -0.44 0.16 0.16 0.16 0.16 -2.34 -2.34 -2.34 -- -- -- n 1 1 1 0 0 0 0 0 0 -- -- 3.6864 N 130 95 47 95 47 23 11 5 2 -- -- Error (%) -0.07 0 0 0 0 0 0 0 0 -- --
o (MHz) 4 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 1 0 0 0 0 0 -- 0 -- N 141 103 51 103 51 25 12 -- -- 1 -- Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 -- -- 0 -- n 1 1 1 0 0 0 0 0 0 0 0 4.9152 N 174 127 63 127 63 31 15 7 3 -- 1 Error (%) -0.26 0 0 0 0 0 0 0 0 -- 0 n 1 1 1 1 0 0 0 0 0 0 0 N 177 129 64 32 64 32 15 7 3 -- 1 5 Error (%) -0.25 0.16 0.16 1.36 0.16 -1.36 1.73 1.73 1.73 -- 1.73 n 1 1 1 1 0 0 0 0 0 0 -- N 212 155 77 38 77 38 19 9 4 2 -- 6 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 -2.34 0 --
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Table 14.4 Examples of BRR Settings in Asynchronous Mode (When oP = o/2) (cont)
o (MHz) 6.144 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 1 1 0 0 0 0 0 0 -- N 217 159 79 39 79 39 19 9 4 2 -- Error (%) 0.08 0 0 0 0 0 0 0 0 2.40 -- n 2 1 1 1 0 0 0 0 0 -- 0 7.3728 N 64 191 95 47 95 47 23 11 5 -- 2 Error (%) 0.70 0 0 0 0 0 0 0 0 -- 0 n 2 1 1 1 0 0 0 0 0 0 -- N 70 207 103 51 103 51 25 12 -- 3 -- 8 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -- 0 -- n 2 1 1 1 0 0 0 0 0 0 0 9.8304 N 86 255 127 63 127 63 31 31 15 9 3 Error (%) 0.31 0 0 0 0 0 0 0 0 -1.70 0
o (MHz) 10 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0 1.73 n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 12 Error (%) -0.44 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 0 -2.34 n 2 2 1 1 0 0 0 0 0 0 0 12.288 N 108 79 159 79 159 79 39 19 9 5 4 Error (%) 0.08 0 0 0 0 0 0 0 0 2.40 0 n 2 2 1 1 0 0 0 0 0 -- 0 14.7456 N 130 95 191 95 191 95 47 23 11 -- 5 Error (%) -0.07 0 0 0 0 0 0 0 0 -- 0
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Table 14.4 Examples of BRR Settings in Asynchronous Mode (When oP = o/2) (cont)
o (MHz) 16 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 -- N 141 103 207 103 207 103 51 25 12 7 -- Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0 --
Legend: Blank: No setting is available --: A setting is available, but error occurs.
343
Note: If possible, the error should be within 1%. B= B: N: F: n: F 64 x 22n-1 x (N + 1) x 106 N= F 64 x 22n-1 x B x 106 - 1
Bit rate (bits/second) Baud rate generator BRR value (0 N 255) oP (MHz) when n 0, or o (MHz) when n = 0 Baud rate generator input clock (n = 0, 1, 2, 3) The meaning of n is given below. SMR WSCR CKDBL 0 0 0 0 1 1 1 1 Clock o o/4 o/16 o/64 o o/8 o/32 o/128
n 0 1 2 3 0 1 2 3
CKS1 0 0 1 1 0 0 1 1
CKS0 0 1 0 1 0 1 0 1
The bit rate error can be calculated with the formula below. F x 106 (N + 1) x B x 64 x 22n-1 - 1 x 100
Error (%) =
344
Table 14.5 Examples of BRR Settings in Synchronous Mode (When oP = o)
o (MHz) Bit Rate (bits/s) 100 250 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M 2.5 M 4M Legend Blank: No setting is available --: A setting is available, but error occurs. *: Continuous transfer is not possible 2 n -- 2 1 1 0 0 0 0 0 0 0 0 N -- 124 249 124 199 99 49 19 9 4 1 0* n -- 2 2 1 1 0 0 0 0 0 0 0 0 4 N -- 249 124 249 99 199 99 39 19 9 3 1 0* n -- -- -- -- 1 0 0 0 0 -- 0 -- -- 5 N -- -- -- -- 124 249 124 49 24 -- 4 -- -- n -- 3 2 2 1 1 0 0 0 0 0 0 0 8 N -- 124 249 124 199 99 199 79 39 19 7 3 1 n -- -- -- -- 1 1 0 0 0 0 0 0 -- 0 10 N -- -- -- -- 249 124 249 99 49 24 9 4 -- 0* n -- 3 3 2 2 1 1 0 0 0 0 0 0 -- 0 16 N -- 249 124 249 99 199 99 159 79 39 15 7 3 -- 0*
345
Table 14.6 Examples of BRR Settings in Synchronous Mode (When oP = o/2)
o (MHz) Bit Rate (bits/s) 100 250 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M 2.5 M 4M Legend Blank: No setting is available --: A setting is available, but error occurs. *: Continuous transfer is not possible 2 n -- 1 1 -- 0 0 0 0 0 -- 0 -- N -- 249 124 -- 99 49 24 9 4 -- 0* -- n -- 2 1 1 1 0 0 0 0 0 0 -- -- 4 N -- 124 249 124 49 99 49 19 9 4 1 0* -- n -- -- -- -- -- 0 -- 0 -- -- -- -- 5 N -- -- -- -- -- 124 -- 24 -- -- -- -- n -- 2 2 1 1 1 0 0 0 0 0 0 0 8 N -- 249 124 249 99 49 99 39 19 9 3 1 0 n -- -- -- -- 1 -- 0 0 0 0 0 -- -- -- -- 10 N -- -- -- -- 124 -- 124 49 24 12 4 -- -- -- -- n -- 3 2 2 1 1 1 0 0 0 0 0 0 -- 16 N -- 124 249 124 199 99 49 79 39 19 7 3 1 --
346
B= B: N: F: n:
F 8x 22n-1 x (N + 1)
x 106
N=
F 8x 22n-1 xB
x 106 - 1
Bit rate (bits/second) Baud rate generator BRR value (0 N 255) oP (MHz) when n 0, or o (MHz) when n = 0 Baud rate generator input clock (n = 0, 1, 2, 3) The meaning of n is given below. SMR WSCR CKDBL 0 0 0 0 1 1 1 1 Clock o o/4 o/16 o/64 o o/8 o/32 o/128
n 0 1 2 3 0 1 2 3
CKS1 0 0 1 1 0 0 1 1
CKS0 0 1 0 1 0 1 0 1
347
14.2.9
Bit
Serial/Timer Control Register (STCR)
7 RING 6 CMPF 0 R/(W)* 5 CMPIE 0 R/W 4 LOAD 1 (W) 3 MARK 1 (W) 2 -- 1 -- 1 ICKS1 0 R/W 0 ICKS0 0 R/W
Initial value Read/Write
0 R/W
Note: * Software can write a 0 in bit 6 to clear the flag, but cannot write a 1 in this bit.
STCR is an 8-bit readable/writable register that controls the SCI operating mode, selects the TCNT clock source in the 8-bit timers, and controls DTU channel B. STCR is initialized to H'1C by a reset. Bits 7 to 3--DTU Channel B Control: These bits control DTU channel B. For details, see section 5, Data Transfer Unit. Bit 2--Reserved: This bit cannot be modified and is always read as 1. Bits 1 and 0--Internal Clock Source Select 1 and 0 (ICKS1, ICKS0): These bits select the clock input to the timer counters (TCNT) in the 8-bit timers. For details, see section 11.2.3, Timer Control Register. 14.2.10
Bit
Serial Communication Mode Register (SCMR)
7 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 SDIR 0 R/W 2 SINV 0 R/W 1 -- 1 -- 0 SMIF 0 R/W
Initial value Read/Write
1 --
SCMR is an 8-bit readable/writable register that selects the SCI0 interface function. SCMR is initialized to H'F2 by a reset and in the standby modes. Bits 7 to 4--Reserved: These bits cannot be modified and are always read as 1.
348
Bit 3--Data Transfer Direction (SDIR): Selects the serial/parallel conversion format.
Bit 3 SDIR 0 Description TDR contents are transmitted LSB-first. Receive data is stored in RDR LSB-first. 1 TDR contents are transmitted MSB-first. Receive data is stored in RDR MSB-first. (Initial value)
Bit 2--Data Invert (SINV): Specifies inversion of the data logic level. Inversion by the SINV bit applies only to data bits D7 to D0. To invert the parity bit, the O/E bit in SMR must be inverted.
Bit 2 SINV 0 Description TDR contents are transmitted as they are. Receive data is stored in RDR as it is. 1 TDR contents are inverted before being transmitted. Receive data is stored in RDR in inverted form. (Initial value)
Bit 1--Reserved: This bit cannot be modified and is always read as 1. Bit 0--Serial Communication Mode Select (SMIF): This bit is reserved, and should not be written with 1.
Bit 0 SMIF 0 1 Description Normal SCI mode Reserved mode (Initial value)
349
14.3
14.3.1
Operation
Overview
The SCI supports serial data transfer in two modes. In asynchronous mode each character is synchronized individually. In synchronous mode communication is synchronized with a clock signal. The selection of asynchronous or synchronous mode and the communication format depend on SMR settings as indicated in table 14.7. The clock source depends on the settings of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR as indicated in table 14.8. Asynchronous Mode * Data length: 7 or 8 bits can be selected. * A parity bit or multiprocessor bit can be added, and stop bit lengths of 1 or 2 bits can be selected. (These selections determine the communication format and character length.) * Framing errors (FER), parity errors (PER), and overrun errors (ORER) can be detected in receive data, and the line-break condition can be detected. * SCI clock source: An internal or external clock source can be selected. Internal clock: The SCI is clocked by the on-chip baud rate generator and can output a clock signal at the bit-rate frequency. External clock: The external clock frequency must be 16 times the bit rate. (The on-chip baud rate generator is not used.) Synchronous Mode * Communication format: The data length is 8 bits. * Overrun errors (ORER) can be detected in receive data. * SCI clock source: An internal or external clock source can be selected. Internal clock: The SCI is clocked by the on-chip baud rate generator and outputs a serial clock signal to external devices. External clock: The on-chip baud rate generator is not used. The SCI operates on the input serial clock.
350
Table 14.7 Communication Formats Used by SCI
SMR Settings Bit 7 Bit 6 Bit 2 Bit 5 Bit 3 C/A CHR MP PE STOP Mode 0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 -- 0 1 1 0 1 1 -- -- -- -- Synchronous mode 8 bits None Asynchronous mode (multiprocessor format) 7 bits 8 bits Present None 7 bits None Asynchronous mode Communication Format Data MultiproParity Length cessor Bit Bit 8 bits None None Stop Bit Length 1 bit 2 bits Present 1 bit 2 bits 1 bit 2 bits Present 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits None
Table 14.8 SCI Clock Source Selection
SMR Bit 7 C/A 0 SCR Bit 1 CKE1 0 Bit 0 CKE0 0 1 1 0 1 1 0 0 1 1 0 1 External Serial clock input Sync Internal Serial clock output External Mode Async Serial Transmit/Receive Clock Clock Source Internal SCK Pin Function Input/output port (not used by SCI) Serial clock output at bit rate Serial clock input at 16 x bit rate
351
14.3.2
Asynchronous Mode
In asynchronous mode, each transmitted or received character is individually synchronized by framing it with a start bit and stop bit. Full duplex data transfer is possible because the SCI has independent transmit and receive sections. Double buffering in both sections enables the SCI to be programmed for continuous data transfer. Figure 14.2 shows the general format of one character sent or received in asynchronous mode. The communication channel is normally held in the mark state (high). Character transmission or reception starts with a transition to the space state (low). The first bit transmitted or received is the start bit (low). It is followed by the data bits, in which the least significant bit (LSB) comes first. The data bits are followed by the parity or multiprocessor bit, if present, then the stop bit or bits (high) confirming the end of the frame. In receiving, the SCI synchronizes on the falling edge of the start bit, and samples each bit at the center of the bit (at the 8th cycle of the internal serial clock, which runs at 16 times the bit rate).
Idle state (mark) 1 0/1 Parity bit Transmit/receive data 1 bit 7 or 8 bits 0 or 1 bit 1 or 2 bits 1 1
1 0 Start bit
(LSB) D0 D1 D2 D3 D4 D5 D6
(MSB) D7
Stop bit
One unit of transfer data (one character or frame)
Figure 14.2 Data Format in Asynchronous Mode (Example of 8-Bit Data with Parity Bit and Two Stop Bits)
352
Data Format: Table 14.9 lists the data formats that can be sent and received in asynchronous mode. Twelve formats can be selected by bits in the serial mode register. Table 14.9 Data Formats in Asynchronous Mode
SMR Bits CHR 0 0 0 0 1 1 1 1 0 0 1 1 PE 0 0 1 1 0 0 1 1 -- -- -- -- MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 1 S S S S S S S S S S S S 2 3 4 5 6 7 8 9 10
STOP
11
12
8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8-bit data 8-bit data 7-bit data 7-bit data
STOP
STOP STOP
P P
STOP
STOP STOP
STOP STOP
P P
STOP
STOP STOP
MPB STOP
MPB STOP STOP
MPB STOP
MPB STOP STOP
Notes: SMR: S: STOP: P: MPB:
Serial mode register Start bit Stop bit Parity bit Multiprocessor bit
353
Clock: In asynchronous mode it is possible to select either an internal clock created by the on-chip baud rate generator, or an external clock input at the SCK pin. The selection is made by the C/A bit in the serial mode register (SMR) and the CKE1 and CKE0 bits in the serial control register (SCR). Refer to table 14.8. If an external clock is input at the SCK pin, its frequency should be 16 times the desired bit rate. If the internal clock provided by the on-chip baud rate generator is selected and the SCK pin is used for clock output, the output clock frequency is equal to the bit rate, and the clock pulse rises at the center of the transmit data bits. Figure 14.3 shows the phase relationship between the output clock and transmit data.
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
One frame
Figure 14.3 Phase Relationship between Clock Output and Transmit Data (Asynchronous Mode) Transmitting and Receiving Data * SCI Initialization: Before transmitting or receiving, software must clear the TE and RE bits to 0 in the serial control register (SCR), then initialize the SCI as follows. Note: When changing the communication mode or format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (RDR), which retain their previous contents. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCI operation becomes unreliable if the clock is stopped.
354
Initialization
1.
Clear TE and RE bits to 0 in SCR 2. 1 Set CKE1 and CKE0 bits in SCR (leaving TE and RE cleared to 0)
Select interrupts and the clock source in the serial control register (SCR). Leave TE and RE cleared to 0. If clock output is selected, in asynchronous mode, clock output starts immediately after the setting is made in SCR. Select the communication format in the serial mode register (SMR). Write the value corresponding to the bit rate in the bit rate register (BRR). This step is not necessary when an external clock is used. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the serial control register (SCR). Setting TE or RE enables the SCI to use the TxD or RxD pin. Also set the RIE, TIE, TEIE, and MPIE bits as necessary to enable interrupts. The initial states are the mark transmit state, and the idle receive state (waiting for a start bit).
3.
2
Select communication format in SMR
4.
3
Set value in BRR
1 bit interval elapsed? Yes 4
No
Set TE or RE to 1 in SCR, and set RIE, TIE, TEIE, and MPIE as necessary
Start transmitting or receiving
Figure 14.4 Sample Flowchart for SCI Initialization
355
* Transmitting Serial Data: Follow the procedure below for transmitting serial data.
1
Initialize Start transmitting
1.
SCI initialization: the transmit data output function of the TxD pin is selected automatically. Transmit become available 1 frame term after TE bit is set. SCI status check and transmit data write: read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. If a multiprocessor format is selected, after writing the transmit data write 0 or 1 in the multiprocessor bit transfer (MPBT) in SSR. Transition of the TDRE bit from 0 to 1 can be reported by an interrupt.
2. 2 Read TDRE bit in SSR No TDRE = 1? Yes Write transmit data in TDR If using multiprocessor format, select MPBT value in SSR
Clear TDRE bit to 0 Serial transmission End of transmission? Yes Read TEND bit in SSR No No
3. (a) To continue transmitting serial data: read the TDRE bit to check whether it is safe to write; if TDRE = 1, write data in TDR, then clear TDRE to 0. (b) To end serial transmission: end of transmission can be confirmed by checking transition of the TEND bit from 0 to 1. This can be reported by a TEI interrupt. 4. To output a break signal at the end of serial transmission: set the DDR bit to 1 and clear the DR bit to 0 (DDR and DR are I/O port registers), then clear TE to 0 in SCR.
3
TEND = 1? Yes 4 Output break signal? Yes Set DR = 0, DDR = 1 Clear TE bit in SCR to 0
No
End
Figure 14.5 Sample Flowchart for Transmitting Serial Data
356
In transmitting serial data, the SCI operates as follows. 1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from TDR into the transmit shift register (TSR). 2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the TIE bit (TDR-empty interrupt enable) is set to 1 in SCR, the SCI requests a TXI interrupt (TDR-empty interrupt) at this time. Serial transmit data is transmitted in the following order from the TxD pin: a. Start bit: One 0 bit is output. b. Transmit data: Seven or eight bits are output, LSB first. c. Parity bit or multiprocessor bit: One parity bit (even or odd parity) or one multiprocessor bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. d. Stop bit: One or two 1 bits (stop bits) are output. e. Idle state: Output of 1 bits continues until the start bit of the next transmit data. 3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, after loading new data from TDR into TSR and transmitting the stop bit, the SCI begins serial transmission of the next frame. If TDRE is 1, after setting the TEND bit to 1 in SSR and transmitting the stop bit, the SCI continues 1-level output in the mark state, and if the TEIE bit (TSR-empty interrupt enable) in SCR is set to 1, the SCI generates a TEI interrupt request (TSR-empty interrupt).
357
Figure 14.6 shows an example of SCI transmit operation in asynchronous mode.
Start bit 0 D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 D0 D1 Parity Stop bit bit D7 0/1 1
1
Data
Data
1 Idle state (mark)
TDRE TEND
TXI TXI interrupt handler request writes data in TDR and clears TDRE to 0 1 frame
TXI request
TEI request
Figure 14.6 Example of SCI Transmit Operation (8-Bit Data with Parity and One Stop Bit)
358
* Receiving Serial Data: Follow the procedure below for receiving serial data.
1. SCI initialization: the receive data function of the RxD pin is selected automatically. 2. Receive error handling and break detection: if a receive error occurs, read the ORER, PER, and FER bits in SSR to identify the error. After executing the necessary error handling, clear ORER, PER, and FER all to 0. Transmitting and receiving cannot resume if ORER, PER, or FER remains set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. 3. SCI status check and receive data read: read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. Transition of the RDRF bit from 0 to 1 can be reported by an RXI interrupt. 4. To continue receiving serial data: read RDR and clear RDRF to 0 before the stop bit of the current frame is received.
1
Initialize Start receiving
Read ORER, PER, and FER in SSR PER RER ORER = 1? No 3 Read RDRF bit in SSR No Yes
2 Error handling
RDRF = 1? Yes 4
Read receive data from RDR, and clear RDRF bit to 0 in SSR No
Finished receiving? Yes Clear RE to 0 in SCR End
Start error handling Yes Yes
FER = 1? No Discriminate and process error, and clear flags Return
Break? No
Clear RE to 0 in SCR Return
Figure 14.7 Sample Flowchart for Receiving Serial Data
359
In receiving, the SCI operates as follows. 1. The SCI monitors the receive data line and synchronizes internally when it detects a start bit. 2. Receive data is shifted into RSR in order from LSB to MSB. 3. The parity bit and stop bit are received. After receiving these bits, the SCI makes the following checks: a. Parity check: The number of 1s in the receive data must match the even or odd parity setting of the O/E bit in SMR. b. Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first stop bit is checked. c. Status check: RDRF must be 0 so that receive data can be loaded from RSR into RDR. If these checks all pass, the SCI sets RDRF to 1 and stores the received data in RDR. If one of the checks fails (receive error), the SCI operates as indicated in table 14.10. Note: When a receive error flag is set, further receiving is disabled. The RDRF bit is not set to 1. Be sure to clear the error flags. 4. After setting RDRF to 1, if the RIE bit (receive-end interrupt enable) is set to 1 in SCR, the SCI requests an RXI (receive-end) interrupt. If one of the error flags (ORER, PER, or FER) is set to 1 and the RIE bit in SCR is also set to 1, the SCI requests an ERI (receive-error) interrupt. Figure 14.8 shows an example of SCI receive operation in asynchronous mode. Table 14.10 Receive Error Conditions and SCI Operation
Receive Error Overrun error Abbreviation ORER Condition Receiving of next data ends while RDRF is still set to 1 in SSR Stop bit is 0 Parity of receive data differs from even/odd parity setting in SMR Data Transfer Receive data not loaded from RSR into RDR Receive data loaded from RSR into RDR Receive data loaded from RSR into RDR
Framing error Parity error
FER PER
360
1
Start bit 0 D0 D1
Data D7
Parity Stop Start bit bit bit 0/1 1 0 D0 D1
Data D7
Parity Stop bit bit 0/1 0
1 Idle state (mark)
RDRF
FER RXI request 1 frame RXI interrupt handler reads data in RDR and clears RDRF to 0
Framing error, ERI request
Figure 14.8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit) Multiprocessor Communication: The multiprocessor communication function enables several processors to share a single serial communication line. The processors communicate in asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). In multiprocessor communication, each receiving processor is addressed by an ID. A serial communication cycle consists of two cycles: an ID-sending cycle that identifies the receiving processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending cycles. The transmitting processor starts by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. Receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. After receiving data with the multiprocessor bit set to 1, the receiving processor with an ID matching the received data continues to receive further incoming data. Multiple processors can send and receive data in this way. Four formats are available. Parity-bit settings are ignored when a multiprocessor format is selected. For details see table 14.9.
361
Transmitting processor Serial communication line
Receiving processor A (ID = 01)
Receiving processor B (ID = 02)
Receiving processor C (ID = 03)
Receiving processor D (ID = 04)
Serial data
H'01 (MPB = 1) ID-sending cycle: receiving processor address
H'AA (MPB = 0) Data-sending cycle: data sent to receiving processor specified by ID
MPB: Multiprocessor bit
Figure 14.9 Example of Communication among Processors using Multiprocessor Format (Sending Data H'AA to Receiving Processor A) * Transmitting Multiprocessor Serial Data: See figures 14.5 and 14.6.
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* Receiving Multiprocessor Serial Data: Follow the procedure below for receiving multiprocessor serial data.
1
Initialize
1.
SCI initialization: the receive data function of the RxD pin is selected automatically. ID receive cycle: Set the MPIE bit in the serial control register (SCR) to 1. SCI status check and ID check: read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and compare with the processor's own ID. Transition of the RDRF bit from 0 to 1 can be reported by an RXI interrupt. If the ID does not match the receive data, set MPIE to 1 again and clear RDRF to 0. If the ID matches the receive data, clear RDRF to 0. SCI status check and data receiving: read SSR, check that RDRF is set to 1, then read data from the receive data register (RDR) and write 0 in the RDRF bit. Transition of the RDRF bit from 0 to 1 can be reported by an RXI interrupt. Receive error handling and break detection: if a receive error occurs, read the ORER and FER bits in SSR to identify the error. After executing the necessary error handling, clear both ORER and FER to 0. Receiving cannot resume while ORER or FER remains set to 1. When a framing error occurs, the RxD pin can be read to detect the break state.
Start receiving
2.
2
Set MPIE bit to 1 in SCR
3.
Read ORER and FER bits in SSR FER ORER = 1? No 3 Read RDRF bit in SSR 5. No RDRF = 1? Yes Read receive data from RDR No Yes
4.
Own ID? Yes Read ORER and FER bits in SSR FER + ORER = 1? No 4 Read RDRF bit in SSR
Yes
RDRF = 1? Yes
No Start error handling
Read receive data from RDR
5 Error handling FER = 1? No Discriminate and process error, and clear flags Return
Yes
Break? No
Yes
Finished receiving? Yes Clear RE to 0 in SCR
No
Clear RE bit to 0 in SCR Return
End
Figure 14.10 Sample Flowchart for Receiving Multiprocessor Serial Data
363
Figure 14.11 shows an example of an SCI receive operation using a multiprocessor format (8-bit data with multiprocessor bit and one stop bit).
Start bit 0 D0 Stop Start MPB bit bit D7 1 1 0 Stop MPB bit 0 1
1
Data (ID1) D1
Data (Data1) D0 D1 D7
1 Idle state (mark)
MPIE
RDRF
RDR value RXI request, MPIE = 0 RXI handler reads RDR data and clears RDRF to 0
ID1 Not own ID, so MPIE is set to 1 again No RXI request, RDR not updated
(Multiprocessor interrupt) (a) Own ID does not match data
1
Start bit 0 D0
Data (ID2) D1 D7
Stop Start MPB bit bit 1 1 0
Data (Data2) D0 D1 D7
Stop MPB bit 0 1
1 Idle state (mark)
MPIE
RDRF
RDR value
ID1 RXI request, MPIE = 0
ID2 RXI handler reads Own ID, so receiving RDR data and clears continues, with data RDRF to 0 received at each RXI
Data 2 MPIE set to 1 again
(Multiprocessor interrupt) (b) Own ID matches data
Figure 14.11 Example of SCI Receive Operation (Eight-Bit Data with Multiprocessor Bit and One Stop Bit)
364
14.3.3
Synchronous Mode
Overview: In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver share the same clock but are otherwise independent, so full duplex communication is possible. The transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Figure 14.12 shows the general format in synchronous serial communication.
One unit (character or frame) of serial data * Serial clock LSB Serial data Don't care Note: * High except in continuous transmitting or receiving Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care *
Figure 14.12 Data Format in Synchronous Communication In synchronous serial communication, each data bit is sent on the communication line from one falling edge of the serial clock to the next. Data is received in synchronization with the rising edge of the serial clock. In each character, the serial data bits are transmitted in order from LSB (first) to MSB (last). After output of the MSB, the communication line remains in the state of the MSB. * Communication Format: The data length is fixed at eight bits. No parity bit or multiprocessor bit can be added. * Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected by clearing or setting the CKE1 bit in the serial control register (SCR). See table 14.8. When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCI is not transmitting or receiving, the clock signal remains at the high level.
365
Transmitting and Receiving Data * SCI Initialization: The SCI must be initialized in the same way as in asynchronous mode. See figure 14.4. When switching from asynchronous mode to synchronous mode, check that the ORER, FER, and PER bits are cleared to 0. Transmitting and receiving cannot begin if ORER, FER, or PER is set to 1. * Transmitting Serial Data: Follow the procedure below for transmitting serial data.
1
Initialize
1.
SCI initialization: the transmit data output function of the TxD pin is selected automatically. SCI status check and transmit data write: read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. Transition of the TDRE bit from 0 to 1 can be reported by a TXI interrupt.
Start transmitting
2.
2
Read TDRE bit in SSR
No TDRE = 1? Yes Write transmit data in TDR and clear TDRE bit to 0 in SSR Serial transmission End of transmission? Yes No
3. (a) To continue transmitting serial data: read the TDRE bit to check whether it is safe to write; if TDRE = 1, write data in TDR, then clear TDRE to 0. (b) To end serial transmission: end of transmission can be confirmed by checking transition of the TEND bit from 0 to 1. This can be reported by a TEI interrupt.
3
Read TEND bit in SSR No
TEND = 1? Yes Clear TE bit to 0 in SCR
End
Figure 14.13 Sample Flowchart for Serial Transmitting
366
In transmitting serial data, the SCI operates as follows. 1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from TDR into the transmit shift register (TSR). 2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the TIE bit (TDR-empty interrupt enable) in SCR is set to 1, the SCI requests a TXI interrupt (TDR-empty interrupt) at this time. If clock output is selected the SCI outputs eight serial clock pulses, triggered by the clearing of the TDRE bit to 0. If an external clock source is selected, the SCI outputs data in synchronization with the input clock. Data is output from the TxD pin in order from LSB (bit 0) to MSB (bit 7). 3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI loads data from TDR into TSR, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit in SSR to 1, transmits the MSB, then holds the output in the MSB state. If the TEIE bit (transmit-end interrupt enable) in SCR is set to 1, a TEI interrupt (TSR-empty interrupt) is requested at this time. 4. After the end of serial transmission, the SCK pin is held at the high level. Figure 14.14 shows an example of SCI transmit operation.
Serial clock
Serial data
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
TDRE
TEND TXI interrupt handler writes data in TDR and clears TDRE to 0 1 frame TXI request
TEI request
Figure 14.14 Example of SCI Transmit Operation
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* Receiving Serial Data: Follow the procedure below for receiving serial data. When switching from asynchronous mode to synchronous mode, be sure to check that PER and FER are cleared to 0. If PER or FER is set to 1 the RDRF bit will not be set and both transmitting and receiving will be disabled.
1
Initialize Start receiving
1. SCI initialization: the receive data function of the RxD pin is selected automatically. 2. Receive error handling: if a receive error occurs, read the ORER bit in SSR then, after executing the necessary error handling, clear ORER to 0. Neither transmitting nor receiving can resume while ORER remains set to 1. When clock output mode is selected, receiving can be halted temporarily by receiving one dummy byte and causing an overrun error. When preparations to 2 receive the next data are completed, clear the ORER bit to 0. This causes receiving to Error handling resume, so return to the step marked 2 in the flowchart. 3. SCI status check and receive data read: read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. Transition of the RDRF bit from 0 to 1 can be reported by an RXI interrupt. 4. To continue receiving serial data: read RDR and clear RDRF to 0 before the MSB (bit 7) of the current frame is received. No
Read ORER bit in SSR Yes ORER = 1? No 3 Read RDRF bit in SSR No
RDRF = 1? Yes 4 Read receive data from RDR, and clear RDRF bit to 0 in SSR Finished receiving? Yes Clear RE to 0 in SCR End
Start error handling Overrun error handling Clear ORER to 0 in SSR
Return
Figure 14.15 Sample Flowchart for Serial Receiving
368
In receiving, the SCI operates as follows. 1. If an external clock is selected, data is input in synchronization with the input clock. If clock output is selected, as soon as the RE bit is set to 1 the SCI begins outputting the serial clock and inputting data. If clock output is stopped because the ORER bit is set to 1, output of the serial clock and input of data resume as soon as the ORER bit is cleared to 0. 2. Receive data is shifted into RSR in order from LSB to MSB. After receiving the data, the SCI checks that RDRF is 0 so that receive data can be loaded from RSR into RDR. If this check passes, the SCI sets RDRF to 1 and stores the received data in RDR. If the check does not pass (receive error), the SCI operates as indicated in table 14.8. Note: Both transmitting and receiving are disabled while a receive error flag is set. The RDRF bit is not set to 1. Be sure to clear the error flag. 3. After setting RDRF to 1, if the RIE bit (receive-end interrupt enable) is set to 1 in SCR, the SCI requests an RXI (receive-end) interrupt. If the ORER bit is set to 1 and the RIE bit in SCR is set to 1, the SCI requests an ERI (receive-error) interrupt. When clock output mode is selected, clock output stops when the RE bit is cleared to 0 or the ORER bit is set to 1. To prevent clock count errors, it is safest to receive one dummy byte and generate an overrun error. Figure 14.16 shows an example of SCI receive operation.
Serial clock
Serial data
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
RDRF
ORER RXI request RXI interrupt RXI handler reads request data in RDR and clears RDRF to 0 1 frame
Overrun error, ERI request
Figure 14.16 Example of SCI Receive Operation
369
* Transmitting and Receiving Serial Data Simultaneously: Follow the procedure below for transmitting and receiving serial data simultaneously. If clock output mode is selected, output of the serial clock begins simultaneously with serial transmission.
1. SCI initialization: the transmit data output function of the TxD pin and receive data input function of the RxD pin are selected, enabling simultaneous transmitting and receiving. 2. SCI status check and transmit data write: read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. Transition of the TDRE bit from 0 to 1 can be reported by a TXI interrupt. 3. SCI status check and receive data read: read the serial status register (SSR), check that the RDRF bit is 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. Transition of the RDRF bit from 0 to 1 can be reported by an RXI interrupt. 4. Receive error handling: if a receive error occurs, read the ORER bit in SSR then, after executing the necessary error handling, clear ORER to 0. Neither transmitting nor receiving can resume while ORER remains set to 1. 4 No Read RDRF bit in SSR No RDRF = 1? Yes 5 Read receive data from RDR and clear RDRF bit to 0 in SSR End of transmitting and receiving? Yes Clear TE and RE bits to 0 in SCR End 5. To continue transmitting and receiving serial data: read RDR and clear RDRF to 0 before the MSB (bit 7) of the current frame is received. Also read the TDRE bit and check that it is set to 1, indicating that it is safe to write; then write data in TDR and clear TDRE to 0 before the MSB (bit 7) of the current frame is transmitted. No Error handling
1
Initialize Start
2
Read TDRE bit in SSR No TDRE = 1? Yes
3
Write transmit data in TDR and clear TDRE bit to 0 in SSR
Read ORER bit in SSR ORER = 1? Yes
Figure 14.17 Sample Flowchart for Serial Transmitting and Receiving Note: In switching from transmitting or receiving to simultaneous transmitting and receiving, clear both TE and RE to 0, then set both TE and RE to 1. Do not use the BSET instruction for this purpose.
370
14.4
Interrupts
The SCI can request four types of interrupts: ERI, RXI, TXI, and TEI. Table 14.11 indicates the source and priority of these interrupts. The interrupt sources can be enabled or disabled by the TIE, RIE, and TEIE bits in the SCR. Independent signals are sent to the interrupt controller for each interrupt source, except that the receive-error interrupt (ERI) is the logical OR of three sources: overrun error, framing error, and parity error. The TXI interrupt indicates that the next transmit data can be written. The TEI interrupt indicates that the SCI has stopped transmitting data. Table 14.11
Interrupt ERI RXI TXI TEI
SCI Interrupt Sources
Description Receive error interrupt (ORER, FER, or PER) Receive end interrupt (RDRF) TDR-empty interrupt (TDRE) TSR-empty interrupt (TEND) Low Priority High
371
14.5
Application Notes
Application programmers should note the following features of the SCI. TDR Write: The TDRE bit in SSR is simply a flag that indicates that the TDR contents have been transferred to TSR. The TDR contents can be rewritten regardless of the TDRE value. If a new byte is written in TDR while the TDRE bit is 0, before the old TDR contents have been moved into TSR, the old byte will be lost. Software should check that the TDRE bit is set to 1 before writing to the TDR. Multiple Receive Errors: Table 14.12 lists the values of flag bits in the SSR when multiple receive errors occur, and indicates whether the RSR contents are transferred to RDR. Table 14.12 SSR Bit States and Data Transfer when Multiple Receive Errors Occur
SSR Bits Receive error Overrun error Framing error Parity error Overrun and framing errors Overrun and parity errors Framing and parity errors Overrun, framing, and parity errors RDRF 1* 1 0 0 1* 1* 0 1*
1 1 1
ORER 1 0 0 1 1 0 1
FER 0 1 0 1 0 1 1
PER 0 0 1 0 1 1 1
RSR RDR*2 No Yes Yes No No Yes No
Notes: 1. Set to 1 before the overrun error occurs. 2. Yes: The RSR contents are transferred to RDR. No: The RSR contents are not transferred to RDR.
Line Break Detection: When the RxD pin receives a continuous stream of 0's in asynchronous mode (line-break state), a framing error occurs because the SCI detects a 0 stop bit. The value H'00 is transferred from RSR to RDR. Software can detect the line-break state as a framing error accompanied by H'00 data in RDR. The SCI continues to receive data, so if the FER bit is cleared to 0 another framing error will occur.
372
Sampling Timing and Receive Margin in Asynchronous Mode: The serial clock used by the SCI in asynchronous mode runs at 16 times the bit rate. The falling edge of the start bit is detected by sampling the RxD input on the falling edge of this clock. After the start bit is detected, each bit of receive data in the frame (including the start bit, parity bit, and stop bit or bits) is sampled on the rising edge of the serial clock pulse at the center of the bit. See figure 14.18. It follows that the receive margin can be calculated as in equation (1). When the absolute frequency deviation of the clock signal is 0 and the clock duty cycle is 0.5, data can theoretically be received with distortion up to the margin given by equation (2). This is a theoretical limit, however. In practice, system designers should allow a margin of 20% to 30%.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1516 1 2 3 4 5 6 7 8 9 10 11 12 1314 15 16 1 2 3 4 5
Basic clock -7.5 pulses Receive data Start bit +7.5 pulses D0 D1
Sync sampling
Data sampling
Figure 14.18 Sampling Timing (Asynchronous Mode)
M= M: N: D: L: F:
0.5 -
1 D - 0.5 - - (L - 0.5) F 2N N
x 100 [%] .................... (1)
Receive margin Ratio of basic clock to bit rate (N=16) Duty factor of clock--ratio of high pulse width to low width (0.5 to 1.0) Frame length (9 to 12) Absolute clock frequency deviation
When D = 0.5 and F = 0
M = (0.5 - 1/2 x 16) x 100 [%] = 46.875% ......................................... (2)
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Section 15 A/D Converter
15.1 Overview
The H8/3318 includes a 10-bit successive-approximations A/D converter with a selection of up to eight analog input channels. 15.1.1 Features
A/D converter features are listed below. * 10-bit resolution * Eight input channels * High-speed conversion Conversion time: minimum 8.4 s per channel (with 16-MHz system clock) * Two conversion modes Single mode: A/D conversion of one channel Scan mode: continuous conversion on one to four channels * Four 16-bit data registers A/D conversion results are transferred for storage into data registers corresponding to the channels. * Sample-and-hold function * A/D conversion can be externally triggered * A/D interrupt requested at end of conversion At the end of A/D conversion, an A/D end interrupt (ADI) can be requested.
375
15.1.2
Block Diagram
Figure 15.1 shows a block diagram of the A/D converter.
Module data bus Bus interface ADDRC ADDRD ADDRA ADDRB ADCSR + - Analog multiplexer Comparator Control circuit Sample-andhold circuit ADCR
On-chip data bus
AVCC AVSS
10-bit D/A
AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7
Successiveapproximations register
oP/8
oP/16
ADTRG Legend ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD:
ADI interrupt signal
A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D
Figure 15.1 A/D Converter Block Diagram
376
15.1.3
Input Pins
Table 15.1 lists the A/D converter's input pins. The eight analog input pins are divided into two groups: group 0 (AN 0 to AN3), and group 1 (AN4 to AN7). AVCC and AVSS are the power supply for the analog circuits in the A/D converter. Table 15.1 A/D Converter Pins
Pin Name Analog power supply pin Analog ground pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 A/D external trigger input pin Abbreviation AVCC AVSS AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 ADTRG I/O Input Input Input Input Input Input Input Input Input Input Input External trigger input for starting A/D conversion Group 1 analog inputs Function Analog power supply Analog ground and reference voltage Group 0 analog inputs
377
15.1.4
Register Configuration
Table 15.2 summarizes the A/D converter's registers. Table 15.2 A/D Converter Registers
Name A/D data register A (high) A/D data register A (low) A/D data register B (high) A/D data register B (low) A/D data register C (high) A/D data register C (low) A/D data register D (high) A/D data register D (low) A/D control/status register A/D control register Abbreviation ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR R/W R R R R R R R R R/(W)* R/W Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'7F Address H'FFE0 H'FFE1 H'FFE2 H'FFE3 H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFE9
Note: * Only 0 can be written in bit 7, to clear the flag.
378
15.2
15.2.1
Bit
Register Descriptions
A/D Data Registers A to D (ADDRA to ADDRD)
15 14 13 12 11 10 9 8 7 6 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R
AD9 AD8 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- Initial value Read/Write 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bits 15 to 6--A/D Conversion Data (AD9 to AD0): 10-bit data giving an A/D conversion result. Bits 5 to 0--Reserved: These bits cannot be modified and are always read as 0. The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the results of A/D conversion. An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an A/D data register are reserved bits that always read 0. Table 15.3 indicates the pairings of analog input channels and A/D data registers. The CPU can always read and write the A/D data registers. The upper byte can be read directly, but the lower byte is read through a temporary register (TEMP). For details see section 15.3, CPU Interface. The A/D data registers are initialized to H'0000 by a reset and in standby mode. Table 15.3 Analog Input Channels and A/D Data Registers
Analog Input Channel Group 0 AN 0 AN 1 AN 2 AN 3 Group 1 AN 4 AN 5 AN 6 AN 7 A/D Data Register ADDRA ADDRB ADDRC ADDRD
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15.2.2
Bit
A/D Control/Status Register (ADCSR)
7 ADF 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W 3 CKS 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W
Initial value Read/Write
0 R/(W)*
Note: * Only 0 can be written, to clear the flag.
ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D converter. ADCSR is initialized to H'00 by a reset and in standby mode. Bit 7--A/D End Flag (ADF): Indicates the end of A/D conversion.
Bit 7 ADF 0 Description [Clearing condition] Cleared by reading ADF while ADF = 1, then writing 0 in ADF 1 [Setting conditions] 1. Single mode: A/D conversion ends 2. Scan mode: A/D conversion ends in all selected channels (Initial value)
Bit 6--A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the end of A/D conversion.
Bit 6 ADIE 0 1 Description A/D end interrupt request (ADI) is disabled A/D end interrupt request (ADI) is enabled (Initial value)
380
Bit 5--A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 during A/D conversion. It can also be set to 1 by external trigger input at the ADTRG pin.
Bit 5 ADST 0 1 Description A/D conversion is stopped (Initial value)
1. Single mode: A/D conversion starts; ADST is automatically cleared to 0 when conversion ends 2. Scan mode: A/D conversion starts and continues, cycling among the selected channels, until ADST is cleared to 0 by software, by a reset, or by a transition to standby mode
Bit 4--Scan Mode (SCAN): Selects single mode or scan mode. For further information on operation in these modes, see section 15.4, Operation. Clear the ADST bit to 0 before switching the conversion mode.
Bit 4 SCAN 0 1 Description Single mode Scan mode (Initial value)
Bit 3--Clock Select (CKS): Selects the A/D conversion time. Clear the ADST bit to 0 before switching the conversion time. If oP = o/2, the conversion time is twice as long.
Bit 3 CKS 0 1 Description Conversion time = 266 states (maximum) (when oP = o) Conversion time = 134 states (maximum) (when oP = o) (Initial value)
381
Bits 2 to 0--Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit select the analog input channels. Clear the ADST bit to 0 before changing the channel selection.
Group Selection CH2 0 Channel Selection CH1 0 CH0 0 1 1 0 1 1 0 0 1 1 0 1 Single Mode AN 0 (initial value) AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 Description Scan Mode AN 0 AN 0, AN 1 AN 0 to AN2 AN 0 to AN3 AN 4 AN 4, AN 5 AN 4 to AN6 AN 4 to AN7
15.2.3
Bit
A/D Control Register (ADCR)
7 TRGE 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
Initial value Read/Write
0 R/W
ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion. ADCR is initialized to H'7F by a reset and in standby mode. Bit 7--Trigger Enable (TRGE): Enables or disables external triggering of A/D conversion.
Bit 7 TRGE 0 1 Description A/D conversion cannot be externally triggered (Initial value)
Enables start of A/D conversion at the falling edge of the external trigger signal (ADTRG) (A/D conversion can be started by an external trigger or by software.)
Bits 6 to 0--Reserved: These bits cannot be modified, and are always read as 1.
382
15.3
CPU Interface
ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus. Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is read through an 8-bit temporary register (TEMP). An A/D data register is read as follows. When the upper byte is read, the upper-byte value is transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When reading an A/D data register, always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. Figure 15.2 shows the data flow for access to an A/D data register.
Upper-byte read
CPU (H'AA)
Module data bus Bus interface
TEMP (H'40)
ADDRnH (H'AA)
ADDRnL (H'40) (n = A to D)
Lower-byte read
Module data bus Bus interface
CPU (H'40)
TEMP (H'40)
ADDRnH (H'AA)
ADDRnL (H'40) (n = A to D)
Figure 15.2 A/D Data Register Access Operation (Reading H'AA40)
383
15.4
Operation
The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 15.4.1 Single Mode (SCAN = 0)
Single mode should be selected when only one A/D conversion on one channel is required. A/D conversion starts when the ADST bit is set to 1 by software, or by external trigger input. The ADST bit remains set to 1 during A/D conversion and is automatically cleared to 0 when conversion ends. When conversion ends the ADF bit is set to 1. If the ADIE bit is also set to 1, an ADI interrupt is requested at this time. To clear the ADF flag to 0, first read ADCSR, then write 0 in ADF. When the mode or analog input channel must be switched during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the mode or channel is changed. Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure 15.3 shows a timing diagram for this example. 1. Single mode is selected (SCAN = 0), input channel AN1 is selected (CH2 = CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). 2. When A/D conversion is completed, the result is transferred into ADDRB. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. 3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. 4. The A/D interrupt handling routine starts. 5. The routine reads ADCSR, then writes 0 in the ADF flag. 6. The routine reads and processes the conversion result (ADDRB). 7. Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1, A/D conversion starts again and steps 2 to 7 are repeated.
384
Set *
ADIE A/D conversion starts Set * Set * Clear *
ADST Clear *
ADF Idle
State of channel 0 (AN 0) Idle Idle
A/D conversion (1)
State of channel 1 (AN 1) Idle
A/D conversion (2)
Idle
State of channel 2 (AN 2) Idle
State of channel 3 (AN 3)
ADDRA Read conversion result A/D conversion result (1) Read conversion result A/D conversion result (2)
ADDRB
Figure 15.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
ADDRC
ADDRD
Note: * Vertical arrows ( ) indicate instructions executed by software.
385
15.4.2
Scan Mode (SCAN = 1)
Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1 or AN5) starts immediately. A/D conversion continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion results are transferred for storage into the A/D data registers corresponding to the channels. When the mode or analog input channel selection must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the first channel in the group. The ADST bit can be set at the same time as the mode or channel selection is changed. Typical operations when three channels in group 0 (AN0 to AN2) are selected in scan mode are described next. Figure 15.4 shows a timing diagram for this example. 1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1). 2. When A/D conversion of the first channel (AN0) is completed, the result is transferred into ADDRA. Next, conversion of the second channel (AN 1) starts automatically. 3. Conversion proceeds in the same way through the third channel (AN2). 4. When conversion of all selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1, an ADI interrupt is requested at this time. 5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0).
386
Continuous A/D conversion Set *1 Clear*1
ADST Clear*1 A/D conversion time Idle
A/D conversion (1)
ADF Idle A/D conversion (4) Idle
State of channel 0 (AN 0) Idle A/D conversion (2) Idle
State of channel 1 (AN 1) Idle A/D conversion (3)
A/D conversion (5) *2
Idle
State of channel 2 (AN 2) Idle Transfer
Idle
State of channel 3 (AN 3)
ADDRA
A/D conversion result (1)
A/D conversion result (4)
ADDRB
A/D conversion result (2)
Figure 15.4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected)
ADDRC
A/D conversion result (3)
ADDRD
Notes: 1. Vertical arrows ( ) indicate instructions executed by software. 2. Data currently being converted is ignored.
387
15.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 15.5 shows the A/D conversion timing. Table 15.4 indicates the A/D conversion time. As indicated in figure 15.5, the A/D conversion time includes t D and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 15.4. In scan mode, the values given in table 15.4 apply to the first conversion. In the second and subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states when CKS = 1 (when oP = o).
(1) o
Address bus
(2)
Write signal
Input sampling timing
ADF tD t SPL t CONV Legend (1): ADCSR write cycle (2): ADCSR address tD: Synchronization delay tSPL: Input sampling time tCONV: A/D conversion time
Figure 15.5 A/D Conversion Timing
388
Table 15.4 A/D Conversion Time (Single Mode)
CKS = 0 Symbol Synchronization delay Input sampling time* A/D conversion time* tD t SPL t CONV Min 10 -- 259 Typ -- 80 -- Max 17 -- 266 Min 6 -- 131 CKS = 1 Typ -- 40 -- Max 9 -- 134
Notes: Values in the table are numbers of states. * Values when oP = o. If oP = o/2, the values are twice those shown.
15.4.4
External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGE bit is set to 1 in ADCR, external trigger input is enabled at the ADTRG pin. A high-to-low transition at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as if the ADST bit had been set to 1 by software. Figure 15.6 shows the timing.
o
ADTRG
Internal trigger signal
ADST A/D conversion
Figure 15.6 External Trigger Input Timing
389
15.5
Interrupts
The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt request can be enabled or disabled by the ADIE bit in ADCSR.
15.6
Usage Notes
The following points should be noted when using the A/D converter. Setting Range of Analog Power Supply and Other Pins: 1. Analog input voltage range The voltage applied to the ANn analog input pins during A/D conversion should be in the range AVSS ANn AVCC (n = 0 to 7). 2. AVCC and AVSS input voltages AVCC should have the following value: AVSS = VSS . If the A/D converter is not used, the values should be AV CC = VCC and AVSS = VSS . Notes on Board Design: In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (AN0 to AN7), analog reference power supply (AVref), and analog power supply (AVCC) by the analog ground (AVSS ). Also, the analog ground (AVSS) should be connected at one point to a stable digital ground (VSS) on the board. Notes on Noise Countermeasures: A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN7) should be connected between AVCC and AVSS as shown in figure 15.7. Also, the bypass capacitors connected to AVCC, the filter capacitor connected to AN 0 to AN7 must be connected to AV SS . If a filter capacitor is connected as shown in figure 15.7, the input currents at the analog input pins (AN0 to AN7) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants.
390
AVCC
Rin* 2 *1
100 AN0 to AN7 0.1 F
AVSS
Notes:
Figures are reference values. 1. 10 F 0.01 F
2. Rin: Input impedance
Figure 15.7 Example of Analog Input Protection Circuit A/D Conversion Precision Definitions: H8/3318 A/D conversion precision definitions are given below. * Resolution The number of A/D converter digital output codes * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'000) to B'0000000001 (H'001) (see figure 15.9). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'111111111 (H'3FF) (see figure 15.10). * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 15.8).
391
* Nonlinearity error The error with respect to the ideal A/D conversion characteristic between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error. * Absolute precision The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error.
Digital output
H'3FF H'3FE H'3FD H'004 H'003 H'002 H'001 H'000
Ideal A/D conversion characteristic
Quantization error
1 2 1024 1024
1022 1023 FS 1024 1024 Analog input voltage
Figure 15.8 A/D Conversion Precision Definitions (1)
392
Digital output
Full-scale error
Ideal A/D conversion characteristic
Nonlinearity error
Actual A/D conversion characteristic FS Offset error Analog input voltage
Figure 15.9 A/D Conversion Precision Definitions (2) Permissible Signal Source Impedance: H8/3318 analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 10 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 k, charging may be insufficient and it may not be possible to guarantee the A/D conversion precision. However, if a large capacitance is provided externally, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. But since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/sec or greater). When converting a high-speed analog signal, a low-impedance buffer should be inserted.
393
Influences on Absolute Precision: Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVSS. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas.
H8/3318 chip Sensor output impedance, up to 10 k Sensor input Low-pass filter C to 0.1 F Cin = 15 pF
A/D converter equivalent circuit 10 k
20 pF
Figure 15.10 Example of Analog Input Circuit
394
Section 16 RAM
16.1 Overview
The H8/3318 includes 4 kbytes, of on-chip static RAM. The RAM is connected to the CPU via 16bit data bus. Both byte and word access to the on-chip RAM are performed in two states, enabling rapid data transfer and instruction execution. The on-chip RAM is assigned to addresses H'EF80 to H'FF7F in the H8/3318. The RAME bit in the system control register (SYSCR) can enable or disable the on-chip RAM. 16.1.1 Block Diagram
Figure 16.1 is a block diagram of the on-chip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'EF80 H'EF82
H'EF81 H'EF83
On-chip RAM H'FF7E Even address H'FF7F Odd address
Figure 16.1 Block Diagram of On-Chip RAM
395
16.1.2
RAM Enable Bit (RAME) in System Control Register (SYSCR)
The on-chip RAM is enabled or disabled by the RAME (RAM Enable) bit in the system control register (SYSCR).
Bit 7 SSBY Initial value Read/Write 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 XRST 1 R 2 NMIEG 0 R/W 1 HIE 0 R/W 0 RAME 1 R/W
The only bit in the system control register that concerns the on-chip RAM is the RAME bit. See section 3.2, System Control Register, for the other bits. Bit 0--RAM Enable (RAME): This bit enables or disables the on-chip RAM. The RAME bit is initialized to 1 on the rising edge of the RES signal, so a reset enables the onchip RAM. The RAME bit is not initialized in software standby mode.
Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value)
16.2
16.2.1
Operation
Expanded Modes (Modes 1 and 2)
If the RAME bit is set to 1, accesses to addresses H'EF80 to H'FF7F in the H8/3318, are directed to the on-chip RAM. If the RAME bit is cleared to 0, accesses to these addresses are directed to the external data bus. 16.2.2 Single-Chip Mode (Mode 3)
If the RAME bit is set to 1, accesses to addresses H'EF80 to H'FF7F in the H8/3318, are directed to the on-chip RAM. If the RAME bit is cleared to 0, the on-chip RAM data cannot be accessed. Attempted write access has no effect. Attempted read access always results in H'FF data being read.
396
16.3
16.3.1
Application Notes
Note on Initial Values
The initial value of RAM is undetermined after a power-on reset. Areas to be used must be initialized.
397
Section 17 ROM
17.1 Overview
The H8/3318 includes 60 kbytes, of high-speed, on-chip ROM. The on-chip ROM is connected to the CPU via a 16-bit data bus. Both byte data and word data are accessed in two states, enabling rapid data transfer and instruction fetching. The on-chip ROM is enabled or disabled depending on the MCU operating mode, which is determined by the inputs at the mode pins (MD1 and MD0). See table 17.1. Table 17.1 On-Chip ROM Usage in Each MCU Mode
Mode Pins Mode Mode 1 (expanded mode) Mode 2 (expanded mode) Mode 3 (single-chip mode) MD1 0 1 1 MD0 1 0 1 On-Chip ROM Disabled (external addresses) Enabled Enabled
In PROM mode the PROM version (H8/3318 ZTAT) can be programmed with a standard PROM programmer. In the H8/3318, the accessible ROM addresses are H'0000 to H'E77F (59,264 bytes) in mode 2, and H'0000 to H'EF7F (61,312 bytes) in mode 3. For details, see section 3, MCU Operating Modes and Address Space.
399
17.1.1
Block Diagram
Figure 17.1 is a block diagram of the on-chip ROM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'0000 H'0002
H'0001 H'0003
On-chip ROM H'EF7E Even address H'EF7F Odd address
Figure 17.1 Block Diagram of On-Chip ROM (H8/3318 Single-Chip Mode)
400
17.2
17.2.1
PROM Mode (H8/3318)
PROM Mode Setup
In PROM mode, the H8/3318 PROM version suspends its microcomputer functions to allow the on-chip PROM to be programmed. The programming method is the same as for the HN27C101. To select PROM mode, apply the signal inputs listed in table 17.2. Table 17.2 Selection of PROM Mode
Pin Mode pin MD1 Mode pin MD 0 STBY pin Pins P63 and P64 Input Low Low Low High
17.2.2
Socket Adapter Pin Assignments and Memory Map
The H8/3318 PROM version can be programmed with a general-purpose PROM programmer by using a socket adapter to change the pin-out to 32 pins. There are different socket adapters for different packages as listed in table 17.3. Figure 17.2 shows the socket adapter pin assignments. Table 17.3 Socket Adapters
Package 84-pin PLCC 80-pin QFP 80-pin TQFP 84-pin windowed LCC Socket Adapter HS338ESC02H HS338ESH02H -- HS338ESG02H HS3337ESCS1H HS3337ESHS1H HS3337ESNS1H HS3337ESGS1H
The PROM size is 60 kbytes in the H8/3318. Figure 17.3 shows the memory map of the H8/3318 in PROM mode. H'FF data should be specified for unused address areas in the on-chip PROM. When programming with a PROM programmer, limit the program address range to H'0000 to H'EF7F. Specify H'FF data for addresses H'EF80 and above. If these addresses are programmed by mistake, it may become impossible to program or verify the PROM data. The same is true if page programming is attempted. Particular care is required with a plastic package, since the programmed data cannot be erased.
401
H8/3318 FP-80A CP-84 TFP-80C CG-84 1 6 65 66 67 68 69 70 71 72 64 63 62 61 60 59 58 57 55 54 53 52 51 50 49 48 20 19 18 24 25 29 8, 47 5 4 7 38 12, 56, 73 12 17 79 80 81 82 83 84 1 3 78 77 76 75 74 73 72 71 69 68 67 66 65 63 62 61 32 31 30 36 37 42 19, 60 16 15 18 51 24, 41, 64, 70 Pin RES NMI P3 0 P3 1 P3 2 P3 3 P3 4 P3 5 P3 6 P3 7 P1 0 P1 1 P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 P2 0 P2 1 P2 2 P2 3 P2 4 P2 5 P2 6 P2 7 P9 0 P9 1 P9 2 P6 3 P6 4 AV CC VCC MD0 MD1 STBY AV SS Legend VPP: EO7 to EO0: EA16 to EA0: OE: CE: PGM:
EPROM Socket Pin V PP EA 9 EO 0 EO 1 EO 2 EO 3 EO 4 EO 5 EO 6 EO 7 EA 0 EA 1 EA 2 EA 3 EA 4 EA 5 EA 6 EA 7 EA 8 OE EA 10 EA 11 EA 12 EA 13 EA 14 CE EA 16 EA 15 PGM VCC HN27C101 (32 pins) 1 26 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 24 23 25 4 28 29 22 2 3 31 32
VSS
16
2, 4, 23, VSS
Programming power supply (12.5 V) Data input/output Address input Output enable Chip enable Program enable
Note: All pins not listed in this figure should be left open.
Figure 17.2 Socket Adapter Pin Assignments
402
Address in MCU mode H'0000
Address in PROM mode H'0000
On-chip PROM
H'EF7F
H'EF7F
1 output* H'1FFFF
Note: * If this address area is read in PROM mode, the output data is H'FF.
Figure 17.3 H8/3318 Memory Map in PROM Mode
17.3
Programming
The write, verify, and other sub-modes of the PROM mode are selected as shown in table 17.4. Table 17.4 Selection of Sub-Modes in PROM Mode
Sub-Mode Write Verify Programming inhibited CE Low Low Low Low High High OE High Low Low High Low High PGM Low High Low High Low High VPP VPP VPP VPP VCC VCC VCC VCC EO7 to EO0 Data input Data output High impedance EA 16 to EA0 Address input Address input Address input
The H8/3318 PROM has the same standard read/write specifications as the HN27C101 EPROM. Page programming is not supported, however, so do not select page programming mode. PROM programmers that provide only page programming cannot be used. When selecting a PROM programmer, check that it supports a byte-at-a-time high-speed programming mode. Be sure to set the address range to H'0000 to H'EF7F.
403
17.3.1
Programming and Verification
An efficient, high-speed programming procedure can be used to program and verify PROM data. This procedure programs data quickly without subjecting the chip to voltage stress and without sacrificing data reliability. It leaves the data H'FF in unused addresses. Figure 17.4 shows the basic high-speed programming flowchart. Tables 17.5 and 17.6 list the electrical characteristics of the chip in PROM mode. Figure 17.5 shows a program/verify timing chart.
Start
Set program/verify mode VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V Address = 0
n=0 n + 1 n Program tPW = 0.2 ms 5% No Yes n < 25? No
Verify OK? Yes Program tOPW = 0.2n ms No
Address + 1 address
Last address? Yes Set read mode VCC = 5.0 V 0.25 V, VPP = VCC
Error
No go
Read all addresses Go End
Figure 17.4 High-Speed Programming Flowchart
404
Table 17.5 DC Characteristics (when VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, VSS = 0 V, Ta = 25C 5C)
Item Input high voltage Input low voltage Output high voltage Output low voltage EO7 - EO0, EA16 - EA0, OE, CE, PGM EO7 - EO0, EA16 - EA0, OE, CE, PGM EO7 - EO0 EO7 - EO0 Symbol VIH Min 2.4 Typ -- Max VCC + 0.3 Unit V Test Conditions
VIL
- 0.3
--
0.8
V
VOH VOL |ILI|
2.4 -- --
-- -- --
-- 0.45 2
V V A
I OH = -200 A I OL = 1.6 mA Vin = 5.25 V/0.5 V
Input leakage EO7 - EO0, current EA16 - EA0, OE, CE, PGM VCC current VPP current
I CC I PP
-- --
-- --
40 40
mA mA
405
Table 17.6 AC Characteristics (when VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25C 5C)
Item Address setup time OE setup time Data setup time Address hold time Data hold time Data output disable time VPP setup time Program pulse width OE pulse width for overwrite-programming VCC setup time CE setup time Data output delay time Symbol t AS t OES t DS t AH t DH t DF t VPS t PW t OPW t VCS t CES t OE Min 2 2 2 0 2 -- 2 0.19 0.19 2 2 0 Typ -- -- -- -- -- -- -- 0.20 -- -- -- -- Max -- -- -- -- -- 130 -- 0.21 5.25 -- -- 150 Unit s s s s s ns s ms ms s s ns Test Conditions See figure 17.5*
Note: * Input pulse level: 0.8 V to 2.2 V Input rise/fall time 20 ns Timing reference levels: input--1.0 V, 2.0 V; output--0.8 V, 2.0 V
406
Write Address tAS Data tDS VPP VPP VCC VCC + 1 VCC tVCS tVPS Input data tDH
Verify
tAH Output data tDF
VCC
CE tCES PGM tPW OE tOPW tOES tOE
Figure 17.5 PROM Program/Verify Timing
407
17.3.2
Notes on Programming
(1) Program with the specified voltages and timing. The programming voltage (VPP) is 12.5 V. Caution: Applied voltages in excess of the specified values can permanently destroy the chip. Be particularly careful about the PROM programmer's overshoot characteristics. If the PROM programmer is set to HN27C101 specifications, VPP will be 12.5 V. (2) Before writing data, check that the socket adapter and chip are correctly mounted in the PROM writer. Overcurrent damage to the chip can result if the index marks on the PROM programmer, socket adapter, and chip are not correctly aligned. (3) Don't touch the socket adapter or chip while writing. Touching either of these can cause contact faults and write errors. (4) Page programming is not supported. Do not select page programming mode. (5) The PROM size is 60 kbytes. Set the address range to H'0000 to H'EF7F. When programming, specify H'FF data for unused address areas (H'EF80 to H'1FFFF). 17.3.3 Reliability of Programmed Data
An effective way to assure the data holding characteristics of the programmed chips is to bake them at 150C, then screen them for data errors. This procedure quickly eliminates chips with PROM memory cells prone to early failure. Figure 17.6 shows the recommended screening procedure.
408
Write and verify program
Bake with power off 125 to 150C, 24 to 48 Hr
Read and check program VCC = 5 V
Install
Note: The baking time is the time from when the bake-oven reaches the specified temperature.
Figure 17.6 Recommended Screening Procedure If a series of write errors occurs while the same PROM programmer is in use, stop programming and check the PROM programmer and socket adapter for defects. Please inform Hitachi of any abnormal conditions noted during programming or in screening of program data after high-temperature baking. 17.3.4 Erasing Data
Data is erased by exposing the transparent window in the package to ultraviolet light. The erase conditions are shown in table 17.7. Table 17.7 Erase Conditions
Item Ultraviolet wavelength Minimum irradiation Value 253.7nm 15W s/cm2
The erase conditions in table 17.7 can be met by exposure to a 12000 W/cm2 ultraviolet lamp positioned 2 to 3 cm directly above the chip for approximately 20 minutes.
409
17.4
17.4.1
Handling of Windowed Packages
Glass Erasing Window
Rubbing the glass erasing window of a windowed package with a plastic material or touching it with an electrically charged object can create a static charge on the window surface which may cause the chip to malfunction. If the erasing window becomes charged, the charge can be neutralized by a short exposure to ultraviolet light. This returns the chip to its normal condition, but it also reduces the charge stored in the floating gates of the PROM, so it is recommended that the chip be reprogrammed afterward. Accumulation of static charge on the window surface can be prevented by the following precautions: 1. When handling the package, ground yourself. Don't wear gloves. Avoid other possible sources of static charge. 2. Avoid friction between the glass window and plastic or other materials that tend to accumulate static charge. 3. Be careful when using cooling sprays, since they may have slight ion content. 4. Cover the window with an ultraviolet-shield label, preferably a label including a conductive material. Besides protecting the PROM contents from ultraviolet light, the label protects the chip by distributing static charge uniformly. 17.4.2 Handling after Programming
Fluorescent light and sunlight contain small amounts of ultraviolet, so prolonged exposure to these types of light can cause programmed data to invert. In addition, exposure to any type of intense light can induce photoelectric effects that may lead to chip malfunction. It is recommended that after programming the chip, you cover the erasing window with a light-proof label (such as an ultraviolet-shield label). 17.4.3 84-Pin LCC Package
A socket should always be used when the 84-pin LCC package is mounted on a printed-circuit board. Table 17.8 shows the recommended socket. Table 17.8 Recommended Socket for Mounting 84-Pin LCC Package
Manufacturer Sumitomo 3-M Code 284-1273-00-1102J
410
Section 18 Power-Down State
18.1 Overview
The H8/3318 has a power-down state that greatly reduces power consumption by stopping some or all of the chip functions. The power-down state includes three modes: 1. Sleep mode--a software-triggered mode in which the CPU halts but the rest of the chip remains active 2. Software standby mode--a software-triggered mode in which the entire chip is inactive 3. Hardware standby mode--a hardware-triggered mode in which the entire chip is inactive Table 18.1 lists the conditions for entering and leaving the power-down modes. It also indicates the status of the CPU, on-chip supporting modules, etc. in each power-down mode. Table 18.1 Power-Down State
Mode Sleep mode Entering Procedure Clock CPU Execute Run SLEEP instruction Set SSBY Halt bit in SYSCR to 1, then execute SLEEP instruction Halt Halt DTU Run CPU Sup. Reg's. Mod. Held Run RAM Held I/O Ports Held Exiting Methods * Interrupt * RES * STBY Halt Halt Held Halt and Held initialized Held * NMI * IRQ0-IRQ2, IRQ6 * RES * STBY Halt Halt Not held Halt and Held initialized High * STBY and impedance RES state
Software standby mode
Hardware Set STBY standby pin to low mode level
Legend SYSCR: System control register SSBY: Software standby bit
411
18.1.1
System Control Register (SYSCR)
Four of the eight bits in the system control register (SYSCR) control the power-down state. These are bit 7 (SSBY) and bits 6 to 4 (STS2 to STS0). See table 18.2. Table 18.2 System Control Register
Name System control register Abbreviation SYSCR R/W R/W Initial Value H'09 Address H'FFC4
Bit
7 SSBY
6 STS2 0 R/W
5 STS1 0 R/W
4 STS0 0 R/W
3 XRST 1 R
2 NMIEG 0 R/W
1 DPME 0 R/W
0 RAME 1 R/W
Initial value Read/Write
0 R/W
Bit 7--Software Standby (SSBY): This bit enables or disables the transition to software standby mode. On recovery from software standby mode by an external interrupt, SSBY remains set to 1. To clear this bit, software must write a 0.
Bit 7 SSBY 0 1 Description The SLEEP instruction causes a transition to sleep mode The SLEEP instruction causes a transition to software standby mode (Initial value)
Bits 6 to 4--Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the clock settling time when the chip recovers from software standby mode by an external interrupt. During the selected time, the clock oscillator runs but the CPU and on-chip supporting modules remain in standby. Set bits STS2 to STS0 according to the clock frequency to obtain a settling time of at least 8 ms. See table 18.3.
Bit 6 STS2 0 Bit 5 STS1 0 Bit 4 STS0 0 1 1 0 1 1 0 1 412 -- -- Description Settling time = 8,192 states Settling time = 16,384 states Settling time = 32,768 states Settling time = 65,536 states Settling time = 131,072 states Prohibited (Initial value)
18.2
18.2.1
Sleep Mode
Transition to Sleep Mode
When the SSBY bit in the system control register is cleared to 0, execution of the SLEEP instruction causes a transition from the program execution state to sleep mode. After executing the SLEEP instruction, the CPU halts, but the contents of its internal registers remain unchanged. The on-chip supporting modules continue to operate normally. 18.2.2 Exit from Sleep Mode
The chip exits sleep mode when it receives an internal or external interrupt request, or a low input at the RES or STBY pin. Exit by Interrupt: An interrupt releases sleep mode and starts the CPU's interrupt-handling sequence. If an interrupt from an on-chip supporting module is disabled by the corresponding enable/disable bit in the module's control register, the interrupt cannot be requested, so it cannot wake the chip up. Similarly, the CPU cannot be awakened by an interrupt other than NMI if the I (interrupt mask) bit is set when the SLEEP instruction is executed. Exit by RES pin: When the RES pin goes low, the chip exits from sleep mode to the reset state. Exit by STBY pin: When the STBY pin goes low, the chip exits from sleep mode to hardware standby mode.
18.3
18.3.1
Software Standby Mode
Transition to Software Standby Mode
To enter software standby mode, set the standby bit (SSBY) in the system control register (SYSCR) to 1, then execute the SLEEP instruction. In software standby mode, the system clock stops and chip functions halt, including both CPU functions and the functions of the on-chip supporting modules. Power consumption is reduced to an extremely low level. The on-chip supporting modules and their registers are reset to their initial states, but as long as a minimum necessary voltage supply is maintained, the contents of the CPU registers and on-chip RAM remain unchanged.
413
18.3.2
Exit from Software Standby Mode
The chip can be brought out of software standby mode by an input at one of six pins: NMI, IRQ0, IRQ1, IRQ2, IRQ6, RES, or STBY. Exit by Interrupt: When an NMI, IRQ0, IRQ1, IRQ2, or IRQ6 interrupt request signal is input, the clock oscillator begins operating. After the waiting time set in bits STS2 to STS0 of SYSCR, a stable clock is supplied to the entire chip, software standby mode is released, and interrupt exception-handling begins. IRQ3 to IRQ5, IRQ7 interrupts should be disabled before the transition to software standby (clear IRQ3E to IRQ5E, IRQ7E to 0). Exit by RES Pin: When the RES input goes low, the clock oscillator begins operating. When RES is brought to the high level (after allowing time for the clock oscillator to settle), the CPU starts reset exception handling. Be sure to hold RES low long enough for clock oscillation to stabilize. Exit by STBY Pin: When the STBY input goes low, the chip exits from software standby mode to hardware standby mode. 18.3.3 Clock Settling Time for Exit from Software Standby Mode
Set bits STS2 to STS0 in SYSCR as follows: * Crystal oscillator Set STS2 to STS0 for a settling time of at least 8 ms. Table 18.3 lists the settling times selected by these bits at several clock frequencies. * External clock The STS bits can be set to any value. Normally, the minimum value (STS2 = STS1 = STS0 = 0) is recommended. Table 18.3 Times Set by Standby Timer Select Bits (Unit: ms)
Settling Time (States) 8,192 16,384 32,768 65,536 131,072 System Clock Frequency (MHz) 16 0.51 1.0 2.0 4.1 8.2 12 0.65 1.3 2.7 5.5 10.9 10 0.8 1.6 3.3 6.6 13.1 8 1.0 2.0 4.1 8.2 16.4 6 1.3 2.7 5.5 10.9 21.8 4 2.0 4.1 8.2 16.4 32.8 2 4.1 8.2 16.4 32.8 65.5 1 8.2 16.4 32.8 65.5 0.5 16.4 32.8 65.5 131.1
STS2 0 0 0 0 1
STS1 0 0 1 1 0
STS0 0 1 0 1 --
131.1 262.1
Note: Recommended values are printed in boldface.
414
18.3.4
Sample Application of Software Standby Mode
In this example the chip enters the software standby mode when NMI goes low and exits when NMI goes high, as shown in figure 18.1. The NMI edge bit (NMIEG) in the system control register is originally cleared to 0, selecting the falling edge. When NMI goes low, the NMI interrupt handling routine sets NMIEG to 1 (selecting the rising edge), sets SSBY to 1, then executes the SLEEP instruction. The chip enters software standby mode. It recovers from software standby mode on the next rising edge of NMI.
Clock oscillator o NMI NMIEG SSBY
NMI interrupt handler NMIEG = 1 SSBY = 1
Software standby mode (powerdown state)
Settling time
NMI interrupt handler
SLEEP
Figure 18.1 NMI Timing in Software Standby Mode 18.3.5 Application Note
The I/O ports retain their current states in software standby mode. If a port is in the high output state, the current dissipation caused by the high output current is not reduced.
415
18.4
18.4.1
Hardware Standby Mode
Transition to Hardware Standby Mode
Regardless of its current state, the chip enters hardware standby mode whenever the STBY pin goes low. Hardware standby mode reduces power consumption drastically by halting the CPU, stopping all the functions of the on-chip supporting modules, and placing I/O ports in the high-impedance state. The registers of the on-chip supporting modules are reset to their initial values. Only the onchip RAM is held unchanged, provided the minimum necessary voltage supply is maintained. Notes: 1. The RAME bit in the system control register should be cleared to 0 before the STBY pin goes low. 2. Do not change the inputs at the mode pins (MD1, MD0) during hardware standby mode. Be particularly careful not to let both mode pins go low in hardware standby mode, since that places the chip in PROM mode and increases current dissipation. 18.4.2 Recovery from Hardware Standby Mode
Recovery from hardware standby mode requires inputs at both the STBY and RES pins. When the STBY pin goes high, the clock oscillator begins running. The RES pin should be low at this time and should be held low long enough for the clock to stabilize. When the RES pin changes from low to high, the reset sequence is executed and the chip returns to the program execution state.
416
18.4.3
Timing Relationships
Figure 18.2 shows the timing relationships in hardware standby mode. In the sequence shown, first RES goes low, then STBY goes low, at which point the chip enters hardware standby mode. To recover, first STBY goes high, then after the clock settling time, RES goes high.
Clock pulse generator RES
STBY
Clock settling time Restart
Figure 18.2 Hardware Standby Mode Timing
417
Section 19 Electrical Specifications
19.1 Absolute Maximum Ratings
Table 19.1 lists the absolute maximum ratings. Table 19.1 Absolute Maximum Ratings
Item Supply voltage Programming voltage Input voltage Ports 1-6, 8, 9 Port 7 Analog supply voltage Analog input voltage Operating temperature Symbol VCC VPP Vin Vin AVCC VAN Topr Rating -0.3 to +7.0 -0.3 to +13.5 -0.3 to VCC + 0.3 -0.3 to AVCC + 0.3 -0.3 to +7.0 -0.3 to AVCC + 0.3 Regular specifications: -20 to +75 Wide-range specifications: -40 to +85 Storage temperature Tstg -55 to +125 Unit V V V V V V C C C
Note: Exceeding the absolute maximum ratings shown in table 19.1 can permanently destroy the chip.
19.2
19.2.1
Electrical Characteristics
DC Characteristics
Tables 19.2, 19.3, and 19.4 list the DC characteristics of the 5 V, 4 V, and 3 V versions, respectively, and tables 19.5 and 19.6 give the allowable current output values of the 5 V and 4 V, and 3 V versions, respectively.
419
Table 19.2 DC Characteristics (5 V Version) Conditions: VCC = 5.0 V 10%, AVCC = 5.0 V 10%*1, VSS = AVSS = 0 V, Ta = -20 to 75C (regular specifications), Ta = -40 to 85C (wide-range specifications)
Item Schmitt trigger input voltage (1) Symbol Min P86-P80* 2, VT- 1.0 2 P97, P95-P90* , FTCI, FTIA, FTIB, FTIC, -- VT + FTID, FTI, TMCI0, TMCI1, TMRI0, TMRI1, VT+ -V T- 0.4 IRQ6, IRQ7, ETMCI0, ETMCI1, ETMRI0, ETMRI1 RES, STBY, NMI, MD1, MD0, EXTAL P77 - P7 0 Input high voltage Input low voltage (3) Input low voltage Output high voltage Output low voltage Input pins other than (1) and (2) RES, STBY, MD1, MD0 Input pins other than (1) and (3) All output pins VIH VIH VCC - 0.7 Typ -- Max -- Unit V Test Conditions
--
VCC x 0.7
V
--
--
V
Input high voltage (2)
--
VCC + 0.3
V
2.0 2.0
-- --
AVCC + 0.3 V VCC + 0.3 V
VIL
-0.3
--
0.5
V
VIL
-0.3
--
0.8
V
VOH
VCC - 0.5 3.5
-- -- -- -- -- -- --
-- -- 0.4 1.0 10.0 1.0 1.0
V V V V A A A
I OH = -200 A I OH = -1.0 mA I OL = 1.6 mA I OL = 10.0 mA Vin = 0.5 V to VCC - 0.5 V
All output pins P17 - P10, P27 - P20
VOL
-- --
Input leakage RES current STBY, NMI, MD1, MD0 P77 - P70
|Iin|
-- -- --
Vin = 0.5 V to AVCC - 0.5 V
420
Table 19.2 DC Characteristics (5 V Version) (cont)
Item Leakage current in 3-state (off state) Input pull-up MOS current Input capacitance Ports 1, 2, 3, 4, 5, 6, 8, 9 Symbol Min |ITSI| -- Typ -- Max 1.0 Unit A Test Conditions Vin = 0.5 V to VCC - 0.5 V
Ports 1, 2, 3 RES NMI All input pins except RES and NMI
-I P Cin
30 -- -- --
-- -- -- --
250 60 50 15
A pF pF pF
Vin = 0 V Vin = 0 V, f = 1 MHz, Ta = 25C
Current dissipation* 3
Normal operation Sleep mode
I CC
-- -- -- --
27 36 18 24 0.01 -- 2.0 0.01 -- --
45 60 30 40 5.0 20.0 5.0 5.0 5.5 5.5
mA mA mA mA A A mA A V V
f = 12 MHz f = 16 MHz f = 12 MHz f = 16 MHz Ta 50C 50C < Ta
Standby modes*
4
-- --
Analog supply During A/D current conversion Waiting Analog supply voltage* 1
AI CC
-- --
AVCC = 2.0 V to 5.5 V During operation During wait state or when not in use
AVCC
4.5 2.0
RAM standby voltage
VRAM
2.0
--
--
V
Notes: 1. Connect AVCC to the power supply (VCC) and apply between 2.0 V and 5.5 V even when the A/D converter is not used. 2. P86 to P8 0, P97, and P9 5 to P9 0 include peripheral function inputs multiplexed with these pins. 3. Current dissipation values assume that VIH min = VCC - 0.5 V, VIL max = 0.5 V, all output pins are in the no-load state, and all input pull-up transistors are off. 4. For these values it is assumed that V RAM V CC < 4.5 V and VIH min = VCC x 0.9, VIL max = 0.3 V.
421
Table 19.3 DC Characteristics (4 V Version) Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V*1, VSS = AVSS = 0 V, Ta = -20 to 75C (regular specifications), Ta = -40 to 85C (wide-range specifications)
Item Schmitt trigger input voltage (1) P86 - P8 0* 2, P97, P95 - P90* 2, FTCI, FTIA, FTIB, FTIC, FTID, FTI, TMCI0, TMCI1, TMRI0, TMRI1, IRQ6, IRQ7, ETMCI0, ETMCI1, ETMRI0, ETMRI1 Symbol Min VT- VT + 1.0 -- Typ -- -- -- -- -- -- -- Max -- VCC x 0.7 -- -- VCC x 0.7 -- VCC + 0.3 Unit V V V V V V V VCC = 4.0 V to 4.5 V Test Conditions VCC = 4.5 V to 5.5 V
VT+ -V T- 0.4 VT- VT+ 0.8 --
VT+ -V T- 0.3 Input high voltage (2) RES, STBY, NMI, MD1, MD0, EXTAL P77 - P70 Input high voltage Input low voltage (3) Input low voltage Input pins other than (1) and (2) RES, STBY, MD1, MD0 Input pins other than (1) and (3) All output pins VIH VIH VCC - 0.7
2.0 2.0
-- --
AVCC + 0.3 V VCC + 0.3 V
VIL
-0.3
--
0.5
V
VIL
-0.3 -0.3
-- -- -- --
0.8 0.6 -- --
V V V V
VCC = 4.5 V to 5.5 V VCC = 4.0 V to 4.5 V I OH = -200 A I OH = -1.0 mA, VCC = 4.5 V to 5.5 V I OH = -1.0 mA, VCC = 4.0 V to 4.5 V I OL = 1.6 mA I OL = 10.0 mA
Output high voltage
VOH
VCC - 0.5 3.5
2.8
--
--
V
Output low voltage
All output pins P17 - P10, P27 - P20
VOL
-- --
-- --
0.4 1.0
V V
422
Table 19.3 DC Characteristics (4 V Version) (cont)
Item Input leakage RES current STBY, NMI, MD1, MD0 P77 - P70 Leakage current in 3-state (off state) Input pull-up MOS current Ports 1, 2, 3, 4, 5, 6, 8, 9 |ITSI| Symbol Min |Iin| -- -- -- -- Typ -- -- -- -- Max 10.0 1.0 1.0 1.0 Unit A A A A Vin = 0.5 V to AVCC - 0.5 V Vin = 0.5 V to VCC - 0.5 V Test Conditions Vin = 0.5 V to VCC - 0.5 V
Ports 1, 2, 3
-I P
30
--
250
A
Vin = 0 V, VCC = 4.5 V to 5.5 V Vin = 0 V, VCC = 4.0 V to 4.5 V Vin = 0 V, f = 1 MHz, Ta = 25C
20
--
200
A
Input capacitance
RES NMI All input pins except RES and NMI
Cin
-- -- --
-- -- --
60 50 15
pF pF pF
Current dissipation* 3
Normal operation
I CC
-- --
27 36
45 60
mA mA
f = 12 MHz f = 16 MHz, VCC = 4.5 V to 5.5 V f = 12 MHz f = 16 MHz, VCC = 4.5 V to 5.5 V Ta 50C 50C < Ta
Sleep mode
-- --
18 24
30 40
mA mA
Standby modes* 4
-- --
0.01 --
5.0 20.0
A A
423
Table 19.3 DC Characteristics (4 V Version) (cont)
Item Analog supply During A/D current conversion Waiting Analog supply voltage* 1 AVCC Symbol Min AI CC -- -- 4.0 2.0 Typ 2.0 0.01 -- -- Max 5.0 5.0 5.5 5.5 Unit mA A V V AVCC = 2.0 V to 5.5 V During operation During wait state or when not in use Test Conditions
RAM standby voltage
VRAM
2.0
--
--
V
Notes: 1. Connect AVCC to the power supply (VCC) and apply between 2.0 V and 5.5 V even when the A/D converter is not used. 2. P86 to P8 0, P97, and P9 5 to P9 0 include peripheral function inputs multiplexed with these pins. 3. Current dissipation values assume that V IH min = VCC - 0.5 V, VIL max = 0.5 V, all output pins are in the no-load state, and all input pull-up transistors are off. 4. For these values it is assumed that V RAM V CC < 4.0 V and VIH min = VCC x 0.9, VIL max = 0.3 V.
424
Table 19.4 DC Characteristics (3 V Version) Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V*1, VSS = AVSS = 0 V, Ta = -20 to 75C
Item Schmitt trigger input voltage (1) Symbol Min VCC x 0.15 P86-P80* 2, VT- P97, P95-P90* 2, FTCI, FTIA, FTIB, FTIC, -- VT + FTID, FTI, TMCI0, TMCI1, TMRI0, TMRI1, VT+ -V T- 0.2 IRQ6, IRQ7, ETMCI0, ETMCI1, ETMRI0, ETMRI1 RES, STBY, NMI, MD1, MD0, EXTAL P77 - P70 Input high voltage Input low voltage (3) Input low voltage Output high voltage Output low voltage Input pins other than (1) and (2) RES, STBY, MD1, MD0 Input pins other than (1) and (3) All output pins VIH VIH VCC x 0.9 Typ -- Max -- Unit V Test Conditions
--
VCC x 0.7
V
--
--
V
Input high voltage (2)
--
VCC + 0.3
V
VCC x 0.7 VCC x 0.7
-- --
AVCC + 0.3 V VCC + 0.3 V
VIL
-0.3
--
VCC x 0.1
V
VIL
-0.3
--
VCC x 0.15 V
VOH
VCC - 0.5 VCC - 1.0
-- -- -- -- -- -- --
-- -- 0.4 0.4 10.0 1.0 1.0
V V V V A A A
I OH = -200 A I OH = -1.0 mA I OL = 0.8 mA I OL = 1.6 mA Vin = 0.5 V to VCC - 0.5 V
All output pins P17 - P10, P27 - P20
VOL
-- --
Input leakage RES current STBY, NMI, MD1, MD0 P77 - P70
|Iin|
-- -- --
Vin = 0.5 V to AVCC - 0.5 V
425
Table 19.4 DC Characteristics (3 V Version) (cont)
Item Leakage current in 3-state (off state) Input pull-up MOS current Input capacitance Ports 1, 2, 3, 4, 5, 6, 8, 9 Symbol Min |ITSI| -- Typ -- Max 1.0 Unit A Test Conditions Vin = 0.5 V to VCC - 0.5 V
Ports 1, 2, 3
-I P
3
--
120
A
Vin = 0 V, VCC = 2.7 V to 4.0 V Vin = 0 V, f = 1 MHz, Ta = 25C
RES NMI All input pins except RES and NMI
Cin
-- -- --
-- -- --
60 50 15
pF pF pF
Current dissipation* 3
Normal operation
I CC
--
7
--
mA
f = 6 MHz, VCC = 2.7 V to 3.6 V f = 10 MHz, VCC = 2.7 V to 3.6 V f = 10 MHz, VCC = 4.0 V to 5.5 V f = 6 MHz, VCC = 2.7 V to 3.6 V f = 10 MHz, VCC = 2.7 V to 3.6 V f = 10 MHz, VCC = 4.0 V to 5.5 V Ta 50C 50C < Ta
--
12
22
mA
--
25
--
mA
Sleep mode
--
5
--
mA
--
9
16
mA
--
18
--
mA
Standby modes* 4
-- --
0.01 -- 2.0 0.01
5.0 20.0 5.0 5.0
A A mA A
Analog supply During A/D current conversion Waiting
AI CC
-- --
AVCC = 2.0 V to 5.5 V
426
Table 19.4 DC Characteristics (3 V Version) (cont)
Item Analog supply voltage* 1 Symbol Min AVCC 2.7 2.0 Typ -- -- Max 5.5 5.5 Unit V V Test Conditions During operation During wait state or when not in use
RAM standby voltage
VRAM
2.0
--
--
V
Notes: 1. Connect AVCC to the power supply (VCC) and apply between 2.0 V and 5.5 V even when the A/D converter is not used. 2. P86 to P8 0, P97, and P9 5 to P9 0 include peripheral function inputs multiplexed with these pins. 3. Current dissipation values assume that V IH min = VCC - 0.5 V, VIL max = 0.5 V, all output pins are in the no-load state, and all input pull-up transistors are off. 4. For these values it is assumed that V RAM V CC < 2.7 V and VIH min = VCC x 0.9, VIL max = 0.3 V.
427
Table 19.5 Allowable Output Current Values (5 V and 4 V Versions) Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = AVSS = 0 V, Ta = -20 to 75C (regular specifications), Ta = -40 to 85C (wide-range specifications)
Item Allowable output low current (per pin) Allowable output low current (total) Allowable output high current (per pin) Allowable output high current (total) Ports 1 and 2 Other output pins Ports 1 and 2, total Total of all output All output pins Total of all output -I OH -IOH IOL Symbol I OL Min -- -- -- -- -- -- Typ -- -- -- -- -- -- Max 10 2 80 120 2 40 Unit mA mA mA mA mA mA
Table 19.6 Allowable Output Current Values (3 V Version) Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = -20 to 75C
Item Allowable output low current (per pin) Allowable output low current (total) Allowable output high current (per pin) Allowable output high current (total) Ports 1 and 2 Other output pins Ports 1 and 2, total Total of all output All output pins Total of all output -I OH -IOH IOL Symbol I OL Min -- -- -- -- -- -- Typ -- -- -- -- -- -- Max 2 1 40 60 2 30 Unit mA mA mA mA mA mA
428
Notes on Use: To ensure the reliability of the chip, the output current values shown in tables 19.5 and 19.6 should not be exceeded. When directly driving a Darlington transistor or LED, in particular, a current-limiting resistance must be inserted (see figures 19.1 and 19.2).
H8/3318 chip
2 k Port
Darlington transistor
Figure 19.1 Example of Circuit for Driving a Darlington Transistor
H8/3318 chip VCC 600 Ports 1 or 2 LED
Figure 19.2 Example of Circuit for Driving an LED 19.2.2 AC Characteristics
The AC characteristics are listed in three tables. Bus timing parameters are given in table 19.7, control signal timing parameters in table 19.8, timing parameters of the on-chip supporting modules in table 19.9, and external clock output delay time in table 19.10.
429
Table 19.7 Bus Timing Conditions A: VCC = 4.5 V to 5.5 V, VSS = 0 V, o = 2 MHz to maximum operating frequency, Ta = -20 to 75C (regular specifications), Ta = -40 to 85C (wide-range specifications) Conditions B: VCC = 4.0 V to 5.5 V, VSS = 0 V, o = 2 MHz to maximum operating frequency, Ta = -20 to 75C (regular specifications), Ta = -40 to 85C (wide-range specifications) Conditions C: VCC = 2.7 V to 5.5 V, VSS = 0 V, o = 2 MHz to maximum operating frequency, Ta = -20 to 75C
Conditions C 10 MHz Item Clock cycle time Clock pulse width low Clock pulse width high Clock rise time Clock fall time Address delay time Address hold time Symbol tcyc tCL tCH tCr tCf tAD tAH Min 100 30 30 -- -- -- 20 -- -- -- 110 15 65 35 0 -- -- 5 20 40 10 Max 500 -- -- 20 20 50 -- 50 50 50 -- -- -- -- -- 170 75 -- -- -- -- Conditions B 12 MHz Min 83.3 30 30 -- -- -- 15 -- -- -- 90 10 50 20 0 -- -- 5 20 35 10 Max 500 -- -- 10 10 35 -- 35 35 35 -- -- -- -- -- 160 60 -- -- -- -- Conditions A 16 MHz Min 62.5 20 20 -- -- -- 10 -- -- -- 60 10 40 20 0 -- -- 5 20 30 10 Max 500 -- -- 10 10 30 -- 30 30 30 -- -- -- -- -- 110 60 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Fig. 19.5 Test Conditions Fig. 19.4
Address strobe delay time tASD Write strobe delay time Strobe delay time Write strobe pulse width* Address setup time 1* Address setup time 2* Read data setup time Read data hold time* Read data access time* Write data delay time Write data setup time Write data hold time Wait setup time Wait hold time tWSD tSD tWSW tAS1 tAS2 tRDS tRDH tACC tWDD tWDS tWDH tWTS tWTH
Note: * Values at maximum operating frequency
430
Table 19.8 Control Signal Timing Conditions A: VCC = 4.5 V to 5.5 V, VSS = 0 V, o = 2 MHz to maximum operating frequency, Ta = -20 to 75C (regular specifications), Ta = -40 to 85C (wide-range specifications) Conditions B: VCC = 4.0 V to 5.5 V, VSS = 0 V, o = 2 MHz to maximum operating frequency, Ta = -20 to 75C (regular specifications), Ta = -40 to 85C (wide-range specifications) Conditions C: VCC = 2.7 V to 5.5 V, VSS = 0 V, o = 2 MHz to maximum operating frequency, Ta = -20 to 75C
Conditions C 10 MHz Item RES setup time RES pulse width NMI setup time (NMI, IRQ0 to IRQ7) NMI hold time (NMI, IRQ0 to IRQ7) Interrupt pulse width for recovery from software standby mode (NMI, IRQ0 to IRQ2, IRQ6) Crystal oscillator settling time (power-on reset) Crystal oscillator settling time (software standby) Symbol tRESS tRESW tNMIS tNMIH tNMIW Min 300 10 300 10 300 Max -- -- -- -- -- Conditions B 12 MHz Min 200 10 150 10 200 Max -- -- -- -- -- Conditions A 16 MHz Min 200 10 150 10 200 Max -- -- -- -- -- Unit ns tcyc ns ns ns Fig. 19.7 Test Conditions Fig. 19.6
tOSC1 tOSC2
20 8
-- --
20 8
-- --
20 8
-- --
ms ms
Fig. 19.8 Fig. 19.9
431
* Test Conditions for AC Characteristics
5V
RL LSI output pin
RH C
C = 90 pF: Ports 1-4, 6, 9 30 pF: Ports 5, 8 RL = 2.4 k RH = 12 k Input/output timing measurement levels Low: 0.8 V High: 2.0 V
Figure 19.3 Output Load Circuit
432
Table 19.9 Timing Conditions of On-Chip Supporting Modules Conditions A: VCC = 4.5 V to 5.5 V, VSS = 0 V, o = 2 MHz to maximum operating frequency, Ta = -20 to 75C (regular specifications), Ta = -40 to 85C (wide-range specifications) Conditions B: VCC = 4.0 V to 5.5 V, VSS = 0 V, o = 2 MHz to maximum operating frequency, Ta = -20 to 75C (regular specifications), Ta = -40 to 85C (wide-range specifications) Conditions C: VCC = 2.7 V to 5.5 V, VSS = 0 V, o = 2 MHz to maximum operating frequency, Ta = -20 to 75C
Conditions C 10 MHz Item FRT Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width TMR Timer output delay time Timer reset input setup time Timer clock input setup time Timer clock pulse width (single edge) Timer clock pulse width (both edges) Symbol tFTOD tFTIS tFTCS Min -- 80 80 Max 150 -- -- Conditions B 12 MHz Min -- 50 50 Max 100 -- -- Conditions A 16 MHz Min -- 50 50 Max 100 -- -- Unit ns ns ns Fig. 19.11 Test Conditions Fig. 19.10
tFTCWH tFTCWL tTMOD tTMRS
1.5 -- 80
-- 150 --
1.5 -- 50
-- 100 --
1.5 -- 50
-- 100 --
tcyc ns ns Fig. 19.12 Fig. 19.14
tTMCS
80
--
50
--
50
--
ns
Fig. 19.13
tTMCWH
1.5
--
1.5
--
1.5
--
tcyc
tTMCWL
2.5
--
2.5
--
2.5
--
tcyc
433
Table 19.9 Timing Conditions of On-Chip Supporting Modules (cont)
Conditions C 10 MHz Item SCI Symbol Input (Async) tscyc clock (Sync) t scyc cycle Transmit data delay time (Sync) Receive data setup time (Sync) Receive data hold time (Sync) Input clock pulse width Ports Output data delay time Input data setup time tTXD Min 4 6 -- Max -- -- 200 Conditions B 12 MHz Min 4 6 -- Max -- -- 100 Conditions A 16 MHz Min 4 6 -- Max -- -- 100 Unit tcyc tcyc ns Test Conditions Fig. 19.15
tRXS
150
--
100
--
100
--
ns
tRXH
150
--
100
--
100
--
ns
tSCKW tPWD tPRS
0.4 -- 80 80 -- 10 10 10 10 65 35 20
0.6 150 -- -- 100 -- -- -- -- -- -- --
0.4 -- 50 50 -- 10 10 10 10 65 35 20
0.6 100 -- -- 100 -- -- -- -- -- -- --
0.4 -- 50 50 -- 10 10 10 10 65 35 20
0.6 100 -- -- 100 -- -- -- -- -- -- --
tscyc ns ns ns ns ns ns ns ns ns ns ns
Fig. 19.16 Fig. 19.17
Input data hold tPRH time TPC DPRAM read/write cycle Output data delay time Address hold time Chip select hold time Address setup time Chip select setup time DPRAM Write pulse write cycle width Write data setup time tTPD tRSH tCSH tRSS tCSS tDWP tDDW
Fig. 19.18 Fig. 19.19, Fig. 19.20
Fig. 19.19
Write data hold tDDH time
434
Table 19.9 Timing Conditions of On-Chip Supporting Modules (cont)
Conditions C 10 MHz Item DPRAM read cycle Access time Read data delay time Chip select access time CS output floating time OE output floating time DPRAM WRQ output Wait request delay time 1 Wait request delay time 2 Byte access interval 0 Byte access interval 1 Byte access interval 2 Byte access interval 3 Symbol tDAA tDOE tDACS tDCHZ tDOHZ tWTD1 tWTD2 tBYTE0 tBYTE1 tBYTE2 tBYTE3 Min -- -- -- 0 0 -- 20 2 20 9.5 11 Max 100 85 100 50 50 80 -- -- -- -- -- Conditions B 12 MHz Min -- -- -- 0 0 -- 20 2 20 9.5 11 Max 85 85 85 50 50 50 -- -- -- -- -- Conditions A 16 MHz Min -- -- -- 0 0 -- 20 2 20 9.5 11 Max 85 85 85 50 50 50 -- -- -- -- -- Unit ns ns ns ns ns ns ns tcyc ns tcyc tcyc Fig. 19.22 Fig. 19.21 Test Conditions Fig. 19.20
Byte access interval in DPRAM bound buffer mode Byte access interval in DPRAM buffer query mode
Parallel RDY output handshake delay time 1 interface RDY output receive delay time 2 Receive data setup time Receive data hold time Handshake pulse width
tHRDYD1 tHRDYD2 tTDS tTDH tHDWP
-- -- 20 25 300
80 80 -- -- --
-- -- 20 25 300
80 80 -- -- --
-- -- 20 25 300
80 80 -- -- --
ns ns ns ns ns
Fig. 19.23
435
Table 19.9 Timing Conditions of On-Chip Supporting Modules (cont)
Conditions C 10 MHz Item Parallel WRQ output handshake delay time 1 interface WRQ output transmit delay time 2 Symbol tHWRQD1 tHWRQD2 Min -- -- Max 80 80 Conditions B 12 MHz Min -- -- Max 80 80 Conditions A 16 MHz Min -- -- Max 80 80 Unit ns ns Test Conditions Fig. 19.24
Note: Values at maximum operating frequency
Table 19.10 External Clock Output Stabilization Delay Time Conditions: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, VSS = AVSS = 0 V
Item External clock output stabilization delay time Symbol t DEXT* Min 500 Max -- Unit s Notes Fig. 19.25
Note: * t DEXT includes a 10 tcyc RES pulse width (t RESW).
436
19.2.3
A/D Converter Characteristics
Table 19.11 lists the characteristics of the on-chip A/D converter. Table 19.11 A/D Converter Characteristics Conditions A: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0 V, o = 2 MHz to maximum operating frequency, Ta = -20 to 75C (regular specifications), Ta = -40 to 85C (wide-range specifications) Conditions B: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = AVSS = 0 V, o = 2 MHz to maximum operating frequency, Ta = -20 to 75C (regular specifications), Ta = -40 to 85C (wide-range specifications) Conditions C: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, o = 2 MHz to maximum operating frequency, Ta = -20 to 75C
Conditions C 10 MHz Item Resolution Conversion time (single mode)* Analog input capacitance Allowable signal source impedance Nonlinearity error Offset error Full-scale error Quantizing error Absolute accuracy Min 10 -- -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- Max 10 13.4 20 5 6.0 4.0 4.0 0.5 8.0 Min 10 -- -- -- -- -- -- -- -- Conditions B 12 MHz Typ 10 -- -- -- -- -- -- -- -- Max 10 11.2 20 10 3.0 3.5 3.5 0.5 4.0 Min 10 -- -- -- -- -- -- -- -- Conditions A 16 MHz Typ 10 -- -- -- -- -- -- -- -- Max 10 8.4 20 10 3.0 3.5 3.5 0.5 4.0 Unit Bits s pF k LSB LSB LSB LSB LSB
Note: * Values at maximum operating frequency
437
19.3
MCU Operational Timing
This section provides the following timing charts: 19.3.1 19.3.2 19.3.3 19.3.4 19.3.5 19.3.6 19.3.7 19.3.8 19.3.9 19.3.1 Bus Timing Control Signal Timing 16-Bit Free-Running Timer Timing 8-Bit Timer Timing SCI Timing I/O Port Timing TPC Timing DPRAM Timing External Clck Output Timing Bus Timing Figures 19.4 to 19.5 Figures 19.6 to 19.9 Figures 19.10 to 19.11 Figures 19.12 to 19.14 Figures 19.15 and 19.16 Figure 19.17 Figure 19.18 Figure 19.19 to 19.24 Figure 19.25
(1) Basic Bus Cycle (without Wait States) in Expanded Modes
T1 t cyc t CH o t AD t Cf t Cr tCL T2 T3
A15 to A0 t ASD t ASI AS, RD t ACC D7 to D0 (read) t AS2 WR tWDD D7 to D0 (write) t WDS t WDH tRDS tRDH t SD t AH
t WSD tWSW
t SD t AH
Figure 19.4 Basic Bus Cycle (without Wait States) in Expanded Modes
438
(2) Basic Bus Cycle (with 1 Wait State) in Expanded Modes
T1 O T2 TW T3
A15 to A0
AS, RD
D7 to D0 (read) WR
D7 to D0 (write)
t WTS
t WTH
t WTS
t WTH
WAIT
Figure 19.5 Basic Bus Cycle (with 1 Wait State) in Expanded Modes (Modes 1, 2) 19.3.2 Control Signal Timing
(1) Reset Input Timing
o tRESS RES tRESW tRESS
Figure 19.6 Reset Input Timing
439
(2) Interrupt Input Timing
o tNMIS NMI IRQE (edge) tNMIH
tNMIS
IRQL (level)
tNMIW NMI IRQi Note: i = 0 to 7; IRQE: IRQi when edge-sensed; IRQL: IRQi when level-sensed
Figure 19.7 Interrupt Input Timing (3) Clock Settling Timing
o
VCC
STBY
tOSC1
tOSC1
RES
Figure 19.8 Clock Settling Timing
440
(4) Clock Settling Timing for Recovery from Software Standby Mode
o
NMI
IRQ1 (i = 0, 1, 2, 6) tOSC2
Figure 19.9 Clock Settling Timing for Recovery from Software Standby Mode 19.3.3 16-Bit Free-Running Timer Timing
(1) Free-Running Timer Input/Output Timing
o
Free-running timer counter
Compare-match tFTOD
FTOA0, FTOB0, FTOA1, FTOB1
tFTIS
FTI, FTIA, FTIB, FTIC, FTID
Figure 19.10 Free-Running Timer Input/Output Timing
441
(2) External Clock Input Timing for Free-Running Timer
o tFTCS FTCI tFTCWL tFTCWH
Figure 19.11 External Clock Input Timing for Free-Running Timer 19.3.4 8-Bit Timer Timing
(1) 8-Bit Timer Output Timing
o
Timer counter
Compare-match tTMOD
TMO0, TMO1
Figure 19.12 8-Bit Timer Output Timing (2) 8-Bit Timer Clock Input Timing
o tTMCS TMCI0, TMCI1 tTMCWL tTMCWH tTMCS
Figure 19.13 8-Bit Timer Clock Input Timing
442
(3) 8-Bit Timer Reset Input Timing
o tTMRS TMRI0, TMRI1
Timer counter
N
H'00
Figure 19.14 8-Bit Timer Reset Input Timing 19.3.5 Serial Communication Interface Timing
(1) SCI Input/Output Timing
tScyc Serial clock (SCK0, SCK1) Transmit data (TxD0, TxD1) tRXS Receive data (RxD0, RxD1) tRXH
tTXD
Figure 19.15 SCI Input/Output Timing (Synchronous Mode) (2) SCI Input Clock Timing
tSCKW
SCK0, SCK1
tScyc
Figure 19.16 SCI Input Clock Timing
443
19.3.6
I/O Port Timing
Port read/write cycle T1 T2 T3
o tPRS Port 1 to port 9 (input) tPWD Port 1* to port 9 (output) Note: * Except P96 and P77 to P70 tPRH
Figure 19.17 I/O Port Input/Output Timing 19.3.7 Timing Pattern Controller Timing
o tTPD TP
Figure 19.18 Timing Pattern Controller Timing
444
19.3.8
DPRAM Timing
Explanation of Notation in Figure 19.21 and 19.22: The numbers 0, 1, and 2 used to describe a data register state indicate 0, 1, and 2 bytes are available, respectively. They also indicate that the data register is being accessed. (1) DPRAM Write Cycle
RS0-RS2
CS tCSS tRSS WE tDDW DDB0-DDB7 tDDH tDWP tCSH tRSH
Figure 19.19 DPRAM Write Timing
445
(2) DPRAM Read Cycle
RS0-RS2 tDAA CS tCSS tRSS OE tDOE tDACS DDB0-DDB7 tDCHZ tDOHZ tCSH tRSH
Figure 19.20 DPRAM Read Timing (3) WRQ Output Timing
Data register state
1
0
Other than 0
0
WE, OE tWTD1 tWTD2 WRQ tWTD1
Figure 19.21 WRQ Output Timing
446
(4) Strobe Interval, Access Interval
Data register state
2
1
1 tBYTE0
0 tBYTE1
0
WE, OE
Figure 19.22 (a) Strobe Interval and Access Interval (with WRQ)
Data register state
2
1
0
Other than 0 tBYTE2
1
0
WE, OE
Figure 19.22 (b) Access Interval in Bound Buffer Mode (without WRQ)
CS, RS0-RS2
Selected
Not selected tBYTE3
Selected
WE
OE
Figure 19.22 (c) Access Interval during Buffer Query Mode (without WRQ)
447
(5) Receive Timing of Parallel Handshake Interface
o tHDWP WE tHRDYD1 RDY tHRDYD2
DDB0-DDB7 tTOS tTDH
Figure 19.23 Receive Timing in Handshake Mode (6) Transmit Timing of Parallel Handshake Interface
o
OE tHWRQD1 WRQ tHWRQD2
DDB0-DDB7 tDOE tDOHZ
Figure 19.24 Transmit Timing in Handshake Mode
448
19.3.9
External Clock Output Timing
VCC
2.7 V
STBY EXTAL o (internal or external) RES
VIH
tDEXT* Note: * tDEXT includes a 10 tcyc RES pulse width (tRESW).
Figure 19.25 External Clock Output Stabilization Delay Time
449
Appendix A CPU Instruction Set
A.1 Instruction Set List
Operation Notation
Rd8/16 Rs8/16 Rn8/16 CCR N Z V C PC SP #xx:3/8/16 d:8/16 @aa:8/16 + - x / -- General register (destination) (8 or 16 bits) General register (source) (8 or 16 bits) General register (8 or 16 bits) Condition code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data (3, 8, or 16 bits) Displacement (8 or 16 bits) Absolute address (8 or 16 bits) Addition Subtraction Multiplication Division AND logical OR logical Exclusive OR logical Move Not
Condition Code Notation
Modified according to the instruction result * 0 -- Undetermined (unpredictable) Always cleared to 0 Not affected by the instruction result
451
Table A.1
Instruction Set
Addressing Mode/ Instruction Length Operand Size Condition Code No. of States
#xx: 8/16 Rn
Mnemonic
Operation
@Rn @(d:16, Rn) @-Rn/@Rn+ @aa: 8/16 @(d:8, PC) @@aa Implied
I
HNZVC
MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @Rs, Rd MOV.B @(d:16, Rs), Rd MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd MOV.B Rs, @(d:16, Rd) MOV.B Rs, @-Rd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @Rs, Rd
B #xx:8 Rd8 B Rs8 Rd8 B @Rs16 Rd8 B @(d:16, Rs16) Rd8 B @Rs16 Rd8 Rs16+1 Rs16 B @aa:8 Rd8 B @aa:16 Rd8 B Rs8 @Rd16 B Rs8 @(d:16, Rd16) B Rd16-1 Rd16 Rs8 @Rd16 B Rs8 @aa:8 B Rs8 @aa:16 W #xx:16 Rd16 W Rs16 Rd16 W @Rs16 Rd16 W @Rs16 Rd16 Rs16+2 Rs16 W @aa:16 Rd16 W Rs16 @Rd16 W Rd16-2 Rd16 Rs16 @Rd16 W Rs16 @aa:16 W @SP Rd16 SP+2 SP W SP-2 SP Rs16 @SP
2 2 2 4 2 2 4 2 4 2 2 4 4 2 2 4 2 4 2 4 2 4 2 2
---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
0--2 0--2 0--4 0--6 0--6 0--4 0--6 0--4 0--6 0--6 0--4 0--6 0--4 0--2 0--4 0--6 0--6 0--6 0--4 0--6 0--6 0--6 0--6 0--6
MOV.W @(d:16, Rs), Rd W @(d:16, Rs16) Rd16 MOV.W @Rs+, Rd MOV.W @aa:16, Rd MOV.W Rs, @Rd
MOV.W Rs, @(d:16, Rd) W Rs16 @(d:16, Rd16) MOV.W Rs, @-Rd MOV.W Rs, @aa:16 POP Rd PUSH Rs
452
Table A.1
Instruction Set (cont)
Addressing Mode/ Instruction Length Operand Size Condition Code No. of States 2 2 2 2 2 2 2 2 2 2 2 2 2
#xx: 8/16 Rn
Mnemonic
Operation
@Rn @(d:16, Rn) @-Rn/@Rn+ @aa: 8/16 @(d:8, PC) @@aa Implied
I
HNZVC
MOVFPE @aa:16, Rd MOVTPE Rs, @aa:16 ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDX.B #xx:8, Rd ADDX.B Rs, Rd ADDS.W #1, Rd ADDS.W #2, Rd INC.B Rd DAA.B Rd SUB.B Rs, Rd SUB.W Rs, Rd SUBX.B #xx:8, Rd SUBX.B Rs, Rd SUBS.W #1, Rd SUBS.W #2, Rd DEC.B Rd DAS.B Rd NEG.B Rd CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W Rs, Rd MULXU.B Rs, Rd DIVXU.B Rs, Rd
B Not supported B Not supported B Rd8+#xx:8 Rd8 B Rd8+Rs8 Rd8 W Rd16+Rs16 Rd16 B Rd8+#xx:8 +C Rd8 B Rd8+Rs8 +C Rd8 W Rd16+1 Rd16 W Rd16+2 Rd16 B Rd8+1 Rd8 B Rd8 decimal adjust Rd8 B Rd8-Rs8 Rd8 W Rd16-Rs16 Rd16 B Rd8-#xx:8 -C Rd8 B Rd8-Rs8 -C Rd8 W Rd16-1 Rd16 W Rd16-2 Rd16 B Rd8-1 Rd8 B Rd8 decimal adjust Rd8 B 0-Rd8 Rd8 B Rd8-#xx:8 B Rd8-Rs8 W Rd16-Rs16 B Rd8 x Rs8 Rd16 B Rd16/Rs8 Rd16 (RdH: remainder, RdL: quotient) B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 -- -- (2) (2) (2) (2)
-- (1) -- --
------------ 2 ------------ 2 ---- --* -- --2
* (3) 2
-- (1) -- --
------------ 2 ------------ 2 ---- --* -- -- -- --2
*--2
-- (1)
-- -- -- -- -- -- 14 -- -- (6) (7) -- -- 14
AND.B #xx:8, Rd AND.B Rs, Rd
---- ----
0--2 0--2
453
Table A.1
Instruction Set (cont)
Addressing Mode/ Instruction Length Operand Size Condition Code No. of States 2 2 2 2 2 2 2 2
#xx: 8/16 Rn
Mnemonic
Operation
@Rn @(d:16, Rn) @-Rn/@Rn+ @aa: 8/16 @(d:8, PC) @@aa Implied
I
HNZVC 0 0 0 0 0 0 0
OR.B #xx:8, Rd OR.B Rs, Rd XOR.B #xx:8, Rd XOR.B Rs, Rd NOT.B Rd SHAL.B Rd
B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd Rd B C b7 b0 C b7 b0 0 b7 b0 C b7 b0 0
2 2 2 2 2 2
---- ---- ---- ---- ---- ----
0--2 0--2 0--2 0--2 0--2
SHAR.B Rd
B
2
----
SHLL.B Rd
B
C
2
----
SHLR.B Rd
B
0
2
----
ROTXL.B Rd
B
C b7 b0 C b7 b0
2
----
ROTXR.B Rd
B
2
----
ROTL.B Rd
B
C b7 b0 C b7 b0
2
----
ROTR.B Rd
B
2
----
454
Table A.1
Instruction Set (cont)
Addressing Mode/ Instruction Length Operand Size Condition Code No. of States
#xx: 8/16 Rn
Mnemonic
Operation
@Rn @(d:16, Rn) @-Rn/@Rn+ @aa: 8/16 @(d:8, PC) @@aa Implied 4 4 4 4 4 4 4 4 4 4 4 4
I
HNZVC
BSET #xx:3, Rd BSET #xx:3, @Rd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @Rd BSET Rn, @aa:8 BCLR #xx:3, Rd BCLR #xx:3, @Rd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @Rd BCLR Rn, @aa:8 BNOT #xx:3, Rd BNOT #xx:3, @Rd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @Rd BNOT Rn, @aa:8 BTST #xx:3, Rd BTST #xx:3, @Rd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @Rd BTST Rn, @aa:8
B (#xx:3 of Rd8) 1 B (#xx:3 of @Rd16) 1 B (#xx:3 of @aa:8) 1 B (Rn8 of Rd8) 1 B (Rn8 of @Rd16) 1 B (Rn8 of @aa:8) 1 B (#xx:3 of Rd8) 0 B (#xx:3 of @Rd16) 0 B (#xx:3 of @aa:8) 0 B (Rn8 of Rd8) 0 B (Rn8 of @Rd16) 0 B (Rn8 of @aa:8) 0 B (#xx:3 of Rd8) (#xx:3 of Rd8) B (#xx:3 of @Rd16) (#xx:3 of @Rd16) B (#xx:3 of @aa:8) (#xx:3 of @aa:8) B (Rn8 of Rd8) (Rn8 of Rd8) B (Rn8 of @Rd16) (Rn8 of @Rd16) B (Rn8 of @aa:8) (Rn8 of @aa:8) B (#xx:3 of Rd8) Z B (#xx:3 of @Rd16) Z B (#xx:3 of @aa:8) Z B (Rn8 of Rd8) Z B (Rn8 of @Rd16) Z B (Rn8 of @aa:8) Z
2
------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------ 4 4 ------ ------ ------ 4 4 ------ ------ ---- 2 ---- 6 ---- 6 ---- 2 ---- 6 ---- 6
2
2
2
2
2
2
2
455
Table A.1
Instruction Set (cont)
Addressing Mode/ Instruction Length Operand Size Condition Code No. of States 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2
#xx: 8/16 Rn
Mnemonic
Operation
@Rn @(d:16, Rn) @-Rn/@Rn+ @aa: 8/16 @(d:8, PC) @@aa Implied
I
HNZVC
BLD #xx:3, Rd BLD #xx:3, @Rd BLD #xx:3, @aa:8 BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 BIST #xx:3, Rd BIST #xx:3, @Rd BIST #xx:3, @aa:8 BAND #xx:3, Rd BAND #xx:3, @Rd BAND #xx:3, @aa:8 BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 BOR #xx:3, Rd BOR #xx:3, @Rd BOR #xx:3, @aa:8 BIOR #xx:3, Rd BIOR #xx:3, @Rd BIOR #xx:3, @aa:8 BXOR #xx:3, Rd BXOR #xx:3, @Rd BXOR #xx:3, @aa:8 BIXOR #xx:3, Rd
B (#xx:3 of Rd8) C B (#xx:3 of @Rd16) C B (#xx:3 of @aa:8) C B (#xx:3 of Rd8) C B (#xx:3 of @Rd16) C B (#xx:3 of @aa:8) C B C (#xx:3 of Rd8) B C (#xx:3 of @Rd16) B C (#xx:3 of @aa:8) B C (#xx:3 of Rd8) B C (#xx:3 of @Rd16) B C (#xx:3 of @aa:8) B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C
2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2
---------- ---------- ---------- ---------- ---------- ----------
------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ----------
456
Table A.1
Instruction Set (cont)
Addressing Mode/ Instruction Length Operand Size Condition Code No. of States 6 6
Branching Condition
#xx: 8/16 Rn
Mnemonic
Operation
@Rn @(d:16, Rn) @-Rn/@Rn+ @aa: 8/16 @(d:8, PC) @@aa Implied
I
HNZVC
BIXOR #xx:3, @Rd BIXOR #xx:3, @aa:8 BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 JMP @Rn JMP @aa:16 JMP @@aa:8 BSR d:8
B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C -- PC PC+d:8 -- PC PC+2 -- If condition -- is true -- then -- PC PC+d:8 -- else next; -- -- -- -- -- -- -- -- -- -- PC Rn16 -- PC aa:16 -- PC @aa:8 -- SP-2 SP PC @SP PC PC+d:8 -- SP-2 SP PC @SP PC Rn16 -- SP-2 SP PC @SP PC aa:16 CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV = 0 NV = 1 Z (NV) = 0 Z (NV) = 1
4 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 2 2
---------- ----------
------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 6 ------------ 8 ------------ 6
JSR @Rn
2
------------ 6
JSR @aa:16
4
------------ 8
457
Table A.1
Instruction Set (cont)
Addressing Mode/ Instruction Length Operand Size Condition Code No. of States 10 2 2 2 2 2
#xx: 8/16 Rn
Mnemonic
Operation
@Rn @(d:16, Rn) @-Rn/@Rn+ @aa: 8/16 @(d:8, PC) @@aa Implied 2 2
I
HNZVC
JSR @@aa:8
-- SP-2 SP PC @SP PC @aa:8 -- PC @SP SP+2 SP -- CCR @SP SP+2 SP PC @SP SP+2 SP -- Transit to sleep mode. B #xx:8 CCR B Rs8 CCR B CCR Rd8 B CCR#xx:8 CCR B CCR#xx:8 CCR B CCR#xx:8 CCR -- PC PC+2 -- if R4L0 then Repeat @R5 @R6 R5+1 R5 R6+1 R6 R4L-1 R4L Until R4L=0 else next 2 2 2 2 2 2
------------ 8
RTS RTE
2 ------------ 8
SLEEP LDC #xx:8, CCR LDC Rs, CCR STC CCR, Rd ANDC #xx:8, CCR ORC #xx:8, CCR XORC #xx:8, CCR NOP EEPMOV
2 ------------ 2
------------ 2
2 ------------ 2 4 -- -- -- -- -- -- (4)
Notes:
The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. (1) Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0. (2) If the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0. (3) Set to 1 if decimal adjustment produces a carry; otherwise cleared to 0. (4) The number of states required for execution is 4n+8 (n = value of R4L). (5) These instructions are not supported by the H8/3318 Series. (6) Set to 1 if the divisor is negative; otherwise cleared to 0. (7) Set to 1 if the divisor is zero; otherwise cleared to 0.
458
A.2
Operation Code Map
Table A.2 is a map of the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). Some pairs of instructions have identical first bytes. These instructions are differentiated by the first bit of the second byte (bit 7 of the first instruction word). Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1.
459
!

2 3 4 5 6 7 8 9 A B C D E F
460
STC LDC ORC XORC ANDC LDC ADD INC ADDS MOV ADDX DAA ROTXL ROTXR NOT OR XOR AND SUB DEC SUBS CMP SUBX DAS ROTL ROTR NEG MOV BHI BLS BCC*2 BCS*2 BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE RTS BSR RTE JMP JSR BST MOV*1 BCLR BTS BOR BXOR BAND BIST BLD MOV EEPMOV Bit manipulation instructions BIOR BIXOR BIAND BILD ADD ADDX CMP SUBX OR XOR AND MOV
Low
High
0
1
Table A.2
0
NOP
SLEEP
SHLL
SHLR
1
SHAL
SHAR
2
3
4
BRA*2
BRN*2
Operation Code Map
5
MULXU
DIVXU
6
BSET
BNOT
7
8
9
A
B
C
D
E
F
Notes: 1. The MOVFPE and MOVTPE instructions are identical to MOV instructions in the first byte and first bit of the second byte (bits 15 to 7 of the instruction word). The PUSH and POP instructions are identical in machine language to MOV instructions. 2. The BT, BF, BHS, and BLO instructions are identical in machine language to BRA, BRN, BCC, and BCS, respectively.
A.3
Number of States Required for Execution
The tables below can be used to calculate the number of states required for instruction execution. Table A.3 indicates the number of states required for each cycle (instruction fetch, branch address read, stack operation, byte data access, word data access, internal operation). Table A.4 indicates the number of cycles of each type occurring in each instruction. The total number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I x SI + J x SJ + K x SK + L x SL+ M x SM + N x SN Examples: Mode 1 (on-chip ROM disabled), stack located in external memory, 1 wait state inserted in external memory access. 1. BSET #0, @FFC7 From table A.4: I = L = 2, J = K = M = N= 0 From table A.3: SI = 8, SL = 3 Number of states required for execution: 2 x 8 + 2 x 3 =22 2. JSR @@30 From table A.4: I = 2, J = K = 1, L = M = N = 0 From table A.3: SI = SJ = SK = 8 Number of states required for execution: 2 x 8 + 1 x 8 + 1 x 8 = 32 Table A.3 Number of States Taken by Each Cycle in Instruction Execution
Access Location On-Chip Memory SI SJ SK SL SM SN 1 3 6 1 3+m 6 + 2m 1 2 On-Chip Reg. Field 6 External Memory 6 + 2m
Execution Status (Instruction Cycle) Instruction fetch Branch address read Stack operation Byte data access Word data access Internal operation
Note: m: Number of wait states inserted in access to external device.
461
Table A.4
Number of Cycles in Each Instruction
Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 1 2 2 2 2 2 2 1 1 Word Data Internal Access Operation M N
Instruction Mnemonic ADD ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDS ADDX ADDS.W #1/2, Rd ADDX.B #xx:8, Rd ADDX.B Rs, Rd AND AND.B #xx:8, Rd AND.B Rs, Rd ANDC BAND ANDC #xx:8, CCR BAND #xx:3, Rd BAND #xx:3, @Rd BAND #xx:3, @aa:8 Bcc BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 BCLR BCLR #xx:3, Rd BCLR #xx:3, @Rd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @Rd BCLR Rn, @aa:8
Note: All values left blank are zero. 462
Table A.4
Number of Cycles in Each Instruction (cont)
Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L 1 2 1 1 Word Data Internal Access Operation M N
Instruction Mnemonic BIAND BIAND #xx:3, Rd BIAND #xx:3, @Rd
BIAND #xx:3, @aa:8 2 BILD BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 BIOR BIOR #xx:3, Rd BIOR #xx:3, @Rd BIOR #xx:3, @aa:8 BIST BIST #xx:3, Rd BIST #xx:3, @Rd BIST #xx:3, @aa:8 BIXOR BIXOR #xx:3, Rd BIXOR #xx:3, @Rd 1 2 2 1 2 2 1 2 2 1 2
1 1
1 1
2 2
1 1
BIXOR #xx:3, @aa:8 2 BLD BLD #xx:3, Rd BLD #xx:3, @Rd BLD #xx:3, @aa:8 BNOT BNOT #xx:3, Rd BNOT #xx:3, @Rd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @Rd BNOT Rn, @aa:8 BOR BOR #xx:3, Rd BOR #xx:3, @Rd BOR #xx:3, @aa:8 BSET BSET #xx:3, Rd BSET #xx:3, @Rd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @Rd BSET Rn, @aa:8 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2
1 1
2 2
2 2
1 1
2 2
2 2
Note: All values left blank are zero.
463
Table A.4
Number of Cycles in Each Instruction (cont)
Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L 2 1 2 2 1 2 2 1 2 2 1 2 1 1 1 1 1 1 2 2 1 Word Data Internal Access Operation M N
Instruction Mnemonic BSR BST BSR d:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 BTST BTST #xx:3, Rd BTST #xx:3, @Rd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @Rd BTST Rn, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @Rd
BXOR #xx:3, @aa:8 2 CMP CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W Rs, Rd DAA DAS DEC DIVXU EEPMOV INC JMP DAA.B Rd DAS.B Rd DEC.B Rd DIVXU.B Rs, Rd EEPMOV INC.B Rd JMP @Rn JMP @aa:16 JMP @@aa:8 JSR JSR @Rn JSR @aa:16 JSR @@aa:8 LDC LDC #xx:8, CCR LDC Rs, CCR MOV MOV.B #xx:8, Rd MOV.B Rs, Rd 1 1 1 1 1 1 1 2 1 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1
12 2n+2* 1
2 2
2
Notes: All values left blank are zero. * n: Initial value in R4L. Source and destination are accessed n + 1 times each. 464
Table A.4
Number of Cycles in Each Instruction (cont)
Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L 1 2 1 1 2 1 2 1 1 2 2 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 2 2 Word Data Internal Access Operation M N
Instruction Mnemonic MOV MOV.B @Rs, Rd MOV.B @(d:16,Rs), Rd MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd MOV.B Rs, @(d:16, Rd) MOV.B Rs, @-Rd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @Rs, Rd
MOV.W @(d:16, Rs), 2 Rd MOV.W @Rs+, Rd 1
MOV.W @aa:16, Rd 2 MOV.W Rs, @Rd MOV.W Rs, @(d:16, Rd) MOV.W Rs, @-Rd 1 2 1
MOV.W Rs, @aa:16 2 MOVFPE MOVTPE MULXU NEG NOP NOT OR MOVFPE @aa:16, Rd MOVTPE.Rs, @aa:16 MULXU.Rs, Rd NEG.B Rd NOP NOT.B Rd OR.B #xx:8, Rd OR.B Rs, Rd ORC ORC #xx:8, CCR Not supported Not supported 1 1 1 1 1 1 1
12
Note: All values left blank are zero. 465
Table A.4
Number of Cycles in Each Instruction (cont)
Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 2 2 1 1 Word Data Internal Access Operation M N 2 2
Instruction Mnemonic POP PUSH ROTL ROTR ROTXL ROTXR RTE RTS SHAL SHAR SHLL SHLR SLEEP STC SUB POP Rd PUSH Rd ROTL.B Rd ROTR.B Rd ROTXL.B Rd ROTXR.B Rd RTE RTS SHAL.B Rd SHAR.B Rd SHLL.B Rd SHLR.B Rd SLEEP STC CCR, Rd SUB.B Rs, Rd SUB.W Rs, Rd SUBS SUBX SUBS.W #1/2, Rd SUBX.B #xx:8, Rd SUBX.B Rs, Rd XOR XOR.B #xx:8, Rd XOR.B Rs, Rd XORC XORC #xx:8, CCR
Note: All values left blank are zero.
466
Appendix B Register Field
B.1 Register Addresses and Bit Names
Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module External addresses (in expanded modes)
Addr. (Last Register Byte) Name Bit 7 H'80 H'81 H'82 H'83 H'84 H'85 H'86 H'87 H'88 H'89 H'8A H'8B H'8C H'8D H'8E H'8F H'90 H'91 H'92 H'93 H'94 SMR BRR SCR TDR SSR RDR -- -- TIER TCSR FRCH FRCL OCRAH OCRBH H'95 OCRAL OCRBL H'96 H'97 H'98 H'99 TCR TOCR ICRAH ICRAL IEDGA -- -- -- ICIAE ICFA TDRE TIE C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
SCI1
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
RDRF
ORER
FER
PER
TEND
MPB
MPBT
-- -- ICIBE ICFB
-- -- ICICE ICFC
-- -- ICIDE ICFD
-- -- OCIAE OCFA
-- -- OCIBE OCFB
-- -- OVIE OVF
-- -- -- CCLRA FRT0
IEDGB --
IEDGC --
IEDGD OCRS
BUFEA OEA
BUFEB OEB
CKS1 OLVLA
CKS0 OLVLB
Notes: FRT0: Free-running timer 0 SCI1: Serial communication interface 1
467
Addr. (Last Register Byte) Name Bit 7 H'9A H'9B H'9C H'9D H'9E H'9F H'A0 H'A1 H'A2 H'A3 H'A4 H'A5 H'A6 H'A7 H'A8 H'A9 H'AA H'AB H'AC H'AD H'AE H'AF H'B0 H'B1 H'B2 H'B3 H'B4 H'B5 H'B6 H'B7 H'B8 ICRBH ICRBL ICRCH ICRCL ICRDH ICRDL TCR TCSR FRCH FRCL OCRAH OCRAL OCRBH OCRBL ICRH ICRL TCSR/ TCNT TCNT P1PCR P2PCR P3PCR -- P1DDR P2DDR P1DR P2DR P3DDR P4DDR P3DR P4DR P5DDR ICIE ICF
Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module FRT0
OCIEB OCFB
OCIEA OCFA
OVIE OVF
OEB OLVLB
OEA OLVLA
CKS1 IEDG
CKS0 CCLRA
FRT1
WDT
P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR Port 1 P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR Port 2 P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR Port 3 -- -- -- -- -- -- -- -- --
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Port 1 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Port 2 P17 P27 P16 P26 P15 P25 P14 P24 P13 P23 P12 P22 P11 P21 P10 P20 Port 1 Port 2
P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Port 3 P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Port 4 P37 P47 -- P36 P46 -- P35 P45 -- P34 P44 -- P33 P43 -- P32 P42 P31 P41 P30 P40 Port 3 Port 4
P52DDR P51DDR P50DDR Port 5
Notes: FRT0: Free-running timer 0 FRT1: Free-running timer 1 WDT: Watchdog timer
468
Addr. (Last Register Byte) Name Bit 7 H'B9 H'BA H'BB H'BC H'BD H'BE H'BF H'C0 H'C1 H'C2 H'C3 H'C4 H'C5 H'C6 H'C7 H'C8 H'C9 H'CA H'CB H'CC H'CD H'CE P6DDR P5DR P6DR -- P8DDR P7DR P8DR P9DDR P9DR WSCR STCR SYSCR MDCR ISCR IER TCR TCSR TCORA TCORB TCNT NDER2 NDRB*
Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Port 6 -- P67 -- -- P77 -- -- P66 -- -- P65 -- -- P64 -- -- P63 -- P52 P62 -- P51 P61 -- P50 P60 -- Port 5 Port 6 --
P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR Port 8 P76 P86 P75 P85 P74 P84 P73 P83 P72 P82 P71 P81 P70 P80 Port 7 Port 8
P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR Port 9 P97 -- RING SSBY -- P96 -- CMPF STS2 -- P95 CKDBL CMPIE STS1 -- P94 -- LOAD STS0 -- P93 WMS1 MARK XRST -- P92 WMS0 -- NMIEG -- P91 WC1 ICKS1 DPME MDS1 P90 WC0 ICKS0 RAME MDS0 System control
IRQ7SC IRQ6SC IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC IRQ7E CMIEB CMFB IRQ6E CMIEA CMFA IRQ5E OVIE OVF IRQ4E CCLR1 PWME IRQ3E CCLR0 OS3 IRQ2E CKS2 OS2 IRQ1E CKS1 OS1 IRQ0E CKS0 OS0 TMR0
NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 TPC NDR15 NDR15 NDR14 NDR14 NDR6 NDR6 CMIEA CMFA NDR13 NDR13 NDR5 NDR5 OVIE OVF NDR12 NDR12 NDR4 NDR4 CCLR1 PWME NDR11 -- NDR3 -- CCLR0 OS3 NDR10 -- NDR2 -- CKS2 OS2 NDR9 -- NDR1 -- CKS1 OS1 NDR8 -- NDR0 -- CKS0 OS0 TMR1
H'CF
NDRA*
NDR7 NDR7
H'D0 H'D1 H'D2 H'D3 H'D4
TCR TCSR TCORA TCORB TCNT
CMIEB CMFB
Notes: TMR0: 8-bit timer channel 0 TMR1: 8-bit timer channel 1 TPC: Programmable timing pattern controller * The address changes depending on the trigger setting
469
Addr. (Last Register Byte) Name Bit 7 H'D5 H'D6 NDER1 NDRB*
Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 TPC -- -- -- -- -- -- -- -- -- NDR11 -- NDR10 -- NDR9 -- NDR8
H'D7
NDRA*
-- --
-- -- CHR
-- -- PE
-- -- O/E
-- NDR3 STOP
-- NDR2 MP
-- NDR1 CKS1
-- NDR0 CKS0 SCI0
H'D8 H'D9 H'DA H'DB H'DC H'DD H'DE H'DF H'E0 H'E1 H'E2 H'E3 H'E4 H'E5 H'E6 H'E7 H'E8 H'E9 H'EA H'EB H'EC H'ED H'EE H'EF
SMR BRR SCR TDR SSR RDR SCMR --
C/A
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
-- --
-- -- AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE -- --
-- -- AD7 -- AD7 -- AD7 -- AD7 -- ADST -- --
-- -- AD6 -- AD6 -- AD6 -- AD6 -- SCAN -- --
SDIR -- AD5 -- AD5 -- AD5 -- AD5 -- CKS --
SINV -- AD4 -- AD4 -- AD4 -- AD4 -- CH2 --
-- -- AD3 -- AD3 -- AD3 -- AD3 -- CH1 --
SMIF -- AD2 -- AD2 -- AD2 -- AD2 -- CH0 -- A/D
ADDRAH AD9 ADDRAL AD1 ADDRBH AD9 ADDRBL AD1 ADDRCH AD9 ADDRCL AD1 ADDRDH AD9 ADDRDL AD1 ADCSR ADCR TPMR TPCR -- -- -- -- ADF TRGE --
G3NOV G2NOV G1NOV G0NOV TPC
G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Notes: A/D:
Analog-to-Digital converter
SCI0: Serial communication interface 0 TPC: Programmable timing pattern controller * The address changes depending on the trigger setting
470
Addr. (Last Register Byte) Name Bit 7 H'F0 H'F1 H'F2 H'F3 H'F4 H'F5 H'F6 H'F7 H'F8 H'F9 H'FA H'FB H'FC H'FD H'FE H'FF Note: PCCSR IOCR RLARA RLARB CPARB DTARH DTCRA DTARA DTCRB DTARB DTCRC DTARC DPDRWH DPDRWL DPDRRH DPDRRL DTE DTE DTE QREF HSCE
Bit Names Bit 6 EWRQ DPEA Bit 5 Bit 4 Bit 3 Bit 2 MREF RPEC Bit 1 EMWI -- Bit 0 EMRI -- Module DTU
EWAKARERAKAR MWEF DPEB RPEA RPEB
DTIE
BUD2
BUD1
BUD0
SOS2
SOS1
SOS0
DTIE
BUD2
BUD1
BUD0
SOS2
SOS1
SOS0
DTIE
BUD2
BUD1
BUD0
SOS2
SOS1
SOS0
DTU: Data transfer controller
471
B.2
Abbreviation of register name Bit No. Initial value
Register Descriptions
Address onto which register is mapped TIER--Timer Interrupt Enable Register Bit Initial value Read/Write 7 ICIAE 0 R/W 6 ICIBE 0 R/W 5 ICICE 0 R/W 4 ICIDE 0 R/W 3 H'FF90 2 1 OVIE 0 R/W FRT 0 -- 1 -- Bit names (abbreviations). Bits marked "--" are reserved. Name of on-chip supporting module
Register name
OCIAE OCIBE 0 0 R/W R/W
Type of access permitted R Read only W Write only R/W Read or write
Overflow Interrupt Enable 0 Overflow interrupt request is disabled. 1 Overflow interrupt request is enabled. Output Compare Interrupt B Enable 0 Output compare interrupt request B is disabled. 1 Output compare interrupt request B is enabled. Output Compare Interrupt A Enable 0 Output compare interrupt request A is disabled. 1 Output compare interrupt request A is enabled. Input Capture Interrupt D Enable 0 Input capture interrupt request D is disabled. 1 Input capture interrupt request D is enabled.
Full name of bit
Description of bit function
472
SMR--Serial Mode Register
Bit Initial value Read/Write 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W
H'FF88
3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
SCI1
Clock Select 0 0 o clock 0 1 oP/4 clock 1 0 oP/16 clock 1 1 oP/64 clock Multiprocessor Mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Stop Bit Length 0 One stop bit 1 Two stop bits Parity Mode 0 Even parity 1 Odd parity Parity Enable 0 Transmit: No parity bit added. Receive: Parity bit not checked. 1 Transmit: Parity bit added. Receive: Parity bit checked.
Character Length 0 8-bit data length 1 7-bit data length Communication Mode 0 Asynchronous 1 Synchronous
473
BRR--Bit Rate Register
Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W
H'FF89
3 1 R/W 2 1 R/W 1 1 R/W 0 1
SCI1
R/W
Constant that determines the bit rate
474
SCR--Serial Control Register
Bit Initial value Read/Write 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W
H'FF8A
3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W
SCI1
0 CKE0 0 R/W
Clock Enable 0 0 The SCK pin is not used by the SCI. 1 The SCK pin is used for serial clock output. Clock Enable 1 0 Internal clock 1 External clock Transmit End Interrupt Enable 0 TSR-empty interrupt request is disabled. 1 TSR-empty interrupt request is enabled. Multiprocessor Interrupt Enable 0 Multiprocessor receive interrupt function is disabled. 1 Multiprocessor receive interrupt function is enabled. Receive Enable 0 Receive disabled 1 Receive enabled Transmit Enable 0 Transmit disabled 1 Transmit enabled Receive Interrupt Enable 0 Receive interrupt and receive error interrupt requests are disabled. 1 Receive interrupt and receive error interrupt requests are enabled. Transmit Interrupt Enable 0 TDR-empty interrupt request is disabled. 1 TDR-empty interrupt request is enabled.
475
TDR--Transmit Data Register
Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W
H'FF8B
3 1 R/W 2 1 R/W 1 1 R/W 0 1
SCI1
R/W
Transmit data
476
SSR--Serial Status Register
Bit Initial value Read/Write 7 TDRE 1 R/(W) * 6 RDRF 0 R/(W) * 5 ORER 0 R/(W) * 4 FER 0 R/(W) *
H'FF8C
3 PER 0 R/(W) * 2 TEND 1 R 1 MPB 0 R 0
SCI1
MPBT 0 R/W
Multiprocessor Bit Transfer 0 Multiprocessor bit = 0 in transmit data. 1 Multiprocessor bit = 1 in transmit data. Multiprocessor Bit 0 Multiprocessor bit = 0 in receive data. 1 Multiprocessor bit = 1 in receive data. Transmit End 0 Cleared by reading TDRE = 1, then writing 0 in TDRE. 1 Set to 1 when TE = 0, or when TDRE = 1 at the end of character transmission. Parity Error 0 Cleared by reading PER = 1, then writing 0 in PER. 1 Set when a parity error occurs (parity of receive data does not match parity selected by O/E bit in SMR). Framing Error 0 Cleared by reading FER = 1, then writing 0 in FER. 1 Set when a framing error occurs (stop bit is 0). Overrun Error 0 Cleared by reading ORER = 1, then writing 0 in ORER. 1 Set when an overrun error occurs (next data is completely received while RDRF bit is set to 1). Receive Data Register Full 0 Cleared by reading RDRF = 1, then writing 0 in RDRF. Or when RDR is read in the DTU bus cycle. 1 Set when one character is received normally and transferred from RSR to RDR. Transmit Data Register Empty 0 Cleared by reading TDRE = 1, then writing 0 in TDRE. Or when a data is written to TDR in the DTU bus cycle. 1 Set when: 1. Data is transferred from TDR to TSR. 2. TE is cleared while TDRE = 0. Note: * Software can write a 0 in bits 7 to 3 to clear the flags, but cannot write a 1 in these bits.
477
RDR--Receive Data Register
Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R
H'FF8D
3 0 R 2 0 R 1 0 R 0 0 R
SCI1
Receive data
478
TIER--Timer Interrupt Enable Register
Bit Initial value Read/Write 7 ICIAE 0 R/W 6 ICIBE 0 R/W 5 ICICE 0 R/W 4 ICIDE 0 R/W
H'FF90
3 OCIAE 0 R/W 2 OCIBE 0 R/W 1 OVIE 0 R/W 0
FRT0
-- 1 --
Overflow Interrupt Enable 0 Overflow interrupt request is disabled. 1 Overflow interrupt request is enabled. Output Compare Interrupt B Enable 0 Output compare interrupt request B is disabled. 1 Output compare interrupt request B is enabled. Output Compare Interrupt A Enable 0 Output compare interrupt request A is disabled. 1 Output compare interrupt request A is enabled. Input Capture Interrupt D Enable 0 Input capture interrupt request D is disabled. 1 Input capture interrupt request D is enabled. Input Capture Interrupt C Enable 0 Input capture interrupt request C is disabled. 1 Input capture interrupt request C is enabled. Input Capture Interrupt B Enable 0 Input capture interrupt request B is disabled. 1 Input capture interrupt request B is enabled. Input Capture Interrupt A Enable 0 Input capture interrupt request A is disabled. 1 Input capture interrupt request A is enabled.
479
TCSR--Timer Control/Status Register
Bit Initial value Read/Write 7 ICFA 0 R/(W) * 6 ICFB 0 R/(W) * 5 ICFC 0 R/(W) * 4 ICFD 0 R/(W) *
H'FF91
3 OCFA 0 R/(W) * 2 OCFB 0 R/(W) * 1 OVF 0 R/(W) *
FRT0
0 CCLRA 0 R/W
Counter Clear A 0 FRC count is not cleared. 1 FRC count is cleared by compare-match A. Timer Overflow Flag 0 Cleared by reading OVF = 1, then writing 0 in OVF. 1 Set when FRC changes from H'FFFF to H'0000. Output Compare Flag B 0 Cleared by reading OCFB = 1, then writing 0 in OCFB. 1 Set when FRC = OCRB. Output Compare Flag A 0 Cleared by reading OCFA = 1, then writing 0 in OCFA. 1 Set when FRC = OCRA. Input Capture Flag D 0 Cleared by reading ICFD = 1, then writing 0 in ICFD. 1 Set by FTID input. Input Capture Flag C 0 Cleared by reading ICFC = 1, then writing 0 in ICFC. 1 Set by FTIC input. Input Capture Flag B 0 Cleared by reading ICFB = 1, then writing 0 in ICFB. 1 Set when FTIB input causes FRC to be copied to ICRB. Input Capture Flag A 0 Cleared by reading ICFA = 1, then writing 0 in ICFA. 1 Set when FTIA input causes FRC to be copied to ICRA. Note: * Software can write a 0 in bits 7 to 1 to clear the flags, but cannot write a 1 in these bits.
480
FRC (H and L)--Free-Running Counter
Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W Count value
H'FF92, H'FF93
3 0 R/W 2 0 R/W 1 0 R/W
FRT0
0 0 R/W
OCRA (H and L)--Output Compare Register A
Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W
H'FF94, H'FF95
3 1 R/W 2 1 R/W 1 1 R/W
FRT0
0 1 R/W
Continually compared with FRC. OCFA is set to 1 when OCRA = FRC.
OCRB (H and L)--Output Compare Register B
Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W
H'FF94, H'FF95
3 1 R/W 2 1 R/W 1 1 R/W
FRT0
0 1 R/W
Continually compared with FRC. OCFB is set to 1 when OCRB = FRC.
481
TCR--Timer Control Register
Bit Initial value Read/Write 7 IEDGA 0 R/W 6 IEDGB 0 R/W 5 IEDGC 0 R/W 4 IEDGD 0 R/W
H'FF96
3 BUFEA 0 R/W 2 BUFEB 0 R/W 1 CKS1 0 R/W
FRT0
0 CKS0 0 R/W
Clock Select 0 0 Internal clock source: oP/2 0 1 Internal clock source: oP/8 1 0 Internal clock source: oP/32 1 1 External clock source: counted on rising edge Buffer Enable B 0 ICRD is used for input capture D. 1 ICRD is buffer register for input capture B. Buffer Enable A 0 ICRC is used for input capture C. 1 ICRC is buffer register for input capture A. Input Edge Select D 0 Falling edge of FTID is valid. 1 Rising edge of FTID is valid. Input Edge Select C 0 Falling edge of FTIC is valid. 1 Rising edge of FTIC is valid. Input Edge Select B 0 Falling edge of FTIB is valid. 1 Rising edge of FTIB is valid. Input Edge Select A 0 Falling edge of FTIA is valid. 1 Rising edge of FTIA is valid.
482
TOCR--Timer Output Compare Control Register
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 OCRS 0 R/W
H'FF97
3 OEA 0 R/W 2 OEB 0 R/W 1 OLVLA 0 R/W 0
FRT0
OLVLB 0 R/W
Output Level B 0 Compare-match B causes 0 output. 1 Compare-match B causes 1 output. Output Level A 0 Compare-match A causes 0 output. 1 Compare-match A causes 1 output. Output Enable B 0 Output compare B output is disabled. 1 Output compare B output is enabled. Output Enable A 0 Output compare A output is disabled. 1 Output compare A output is enabled. Output Compare Register Select 0 The CPU can access OCRA. 1 The CPU can access OCRB.
483
ICRA (H and L)--Input Capture Register A
Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R
H'FF98, H'FF99
3 0 R 2 0 R 1 0 R
FRT0
0 0 R
Contains FRC count captured on FTIA input.
ICRB (H and L)--Input Capture Register B
Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R
H'FF9A, H'FF9B
3 0 R 2 0 R 1 0 R
FRT0
0 0 R
Contains FRC count captured on FTIB input.
ICRC (H and L)--Input Capture Register C
Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R
H'FF9C, H'FF9D
3 0 R 2 0 R 1 0 R
FRT0
0 0 R
Contains FRC count captured on FTIC input, or old ICRA value in buffer mode.
ICRD (H and L)--Input Capture Register D
Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R
H'FF9E, H'FF9F
3 0 R 2 0 R 1 0 R
FRT0
0 0 R
Contains FRC count captured on FTID input, or old ICRB value in buffer mode.
484
TCR--Timer Control Register
Bit Initial value Read/Write 7 ICIE 0 R/W 6 OCIEB 0 R/W 5 OCIEA 0 R/W 4 OVIE 0 R/W
H'FFA0
3 OEB 0 R/W 2 OEA 0 R/W 1 CKS1 0 R/W
FRT1
0 CKS0 0 R/W
Clock Select 0 0 Internal clock source: oP/2 0 1 Internal clock source: oP/8 1 0 Internal clock source: oP/32 1 1 External clock source: counted on rising edge Output Enable A 0 Output compare A output is disabled. 1 Output compare A output is enabled. Output Enable B 0 Output compare B output is disabled. 1 Output compare B output is enabled. Timer Overflow Interrupt Enable 0 Overflow interrupt request is disabled. 1 Overflow interrupt request is enabled. Output Compare Interrupt Enable A 0 Output compare interrupt request A is disabled. 1 Output compare interrupt request A is enabled. Output Compare Interrupt Enable B 0 Output compare interrupt request B is disabled. 1 Output compare interrupt request B is enabled. Input Capture Interrupt Enable 0 Input capture interrupt request is disabled. 1 Input capture interrupt request is enabled.
485
TCSR--Timer Control Status Register
Bit Initial value Read/Write 7 ICF 0 R/(W) * 6 OCFB 0 R/(W) * 5 OCFA 0 R/(W) * 4 OVF 0 R/(W) *
H'FFA1
3 OLVLB 0 R/W 2 OLVLA 0 R/W 1 IEDG 0 R/W
FRT1
0 CCLRA 0 R/W
Counter Clear A 0 FRC count is not cleared. 1 FRC count is cleared by compare-match A. Input Edge Select 0 FRC value is transferred to ICR at falling edge of FTI 1 FRC value is transferred to ICR at rising edge of FTI Output Level A 0 Compare-match A causes 0 output 1 Compare-match A causes 1 output Output Level B 0 Compare-match B causes 0 output 1 Compare-match B causes 1 output Timer Overflow Flag 0 Cleared by reading OVF = 1, then writing 0 in OVF 1 Set when FRC changes from H'FFFF to H'0000 Output Compare Flag A 0 Cleared by reading OCFA = 1, then writing 0 in OCFA 1 Set when FRC = OCRA Output Compare Flag B 0 Cleared by reading OCFB = 1, then writing 0 in OCFB 1 Set when FRC = OCRB Input Capture Flag 0 Cleared by reading ICF = 1, then writing 0 in ICF 1 Set when FRC value is copied to ICR by input capture signal
Note: * Software can write a 0 to clear the flags, but cannot write a 1 in these bits.
486
FRC (H and L)--Free Running Counter
Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W Count value
H'FFA2, FFA3
3 0 R/W 2 0 R/W 1 0 R/W
FRT1
0 0 R/W
OCRA (H and L)--Output Compare Register A
Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W
H'FFA4, FFA5
3 1 R/W 2 1 R/W 1 1 R/W
FRT1
0 1 R/W
Continually compared with FRC. OCFA is set to 1 when OCRA = FRC.
OCRB (H and L)--Output Compare Register B
Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W
H'FFA6, FFA7
3 1 R/W 2 1 R/W 1 1 R/W
FRT1
0 1 R/W
Continually compared with FRC. OCFB is set to 1 when OCRB = FRC.
ICR (H and L)--Input Capture Register
Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R
H'FFA8, FFA9
3 0 R 2 0 R 1 0 R
FRT1
0 0 R
Contains FRC count captured by internal input capture signal generated from external input signal transition
487
TCSR--Timer Control/Status Register
Bit Initial value Read/Write 7 OVF 0 R/(W)*3 6 WT/IT 0 R/W 5 TME 0 R/W 4 -- 1 --
H'FFAA*1, H'FFAB*2
3 RST/NMI 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0
WDT
CKS0 0 R/W
Clock Select
0 0 0 oP/2 0 0 1 oP/32 0 1 0 oP/64 0 1 1 oP/128 1 0 0 oP/256 1 0 1 oP/512 1 1 0 oP/2048 1 1 1 oP/4096
Reset or NMI Select 0 NMI function enabled 1 Reset function enabled Timer Enable 0 Timer disabled: TCNT is initialized to H'00 and stopped 1 Timer enabled: TCNT runs; CPU interrupts can be requested Timer Mode Select 0 Interval timer mode (OVF interrupt request) 1 Watchdog timer mode (reset or NMI request) Overflow flag 0 Cleared by reading OVF = 1, then writing 1 in OVF 1 Set when TCNT changes from H'FF to H'00
Notes: 1. Read access address. 2. Write address, but write access requires word transfer to H'FFAA. 3. Only 0 can be written, to clear the flag.
488
TCNT--Timer Counter
Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FFAB*
3 0 R/W 2 0 R/W 1 0 R/W 0 0
WDT
R/W
Count value Note: * Write access requires word transfer to H'FFAA.
P1PCR--Port 1 Input Pull-Up Control Register
Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FFAC
3 0 R/W 2 0 R/W 1 0 R/W
Port 1
0 0 R/W
P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR
Port 1 Input Pull-Up Control 0 Input pull-up transistor is off. 1 Input pull-up transistor is on.
P2PCR--Port 2 Input Pull-Up Control Register
Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FFAD
3 0 R/W 2 0 R/W 1 0 R/W
Port 2
0 0 R/W
P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR
Port 2 Input Pull-Up Control 0 Input pull-up transistor is off. 1 Input pull-up transistor is on.
489
P3PCR--Port 3 Input Pull-Up Control Register
Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FFAE
3 0 R/W 2 0 R/W 1 0 R/W
Port 3
0 0 R/W
P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR
Port 3 Input Pull-Up Control 0 Input pull-up transistor is off. 1 Input pull-up transistor is on.
P1DDR--Port 1 Data Direction Register
Bit Mode 1 Initial value Read/Write Modes 2 and 3 Initial value Read/Write 0 W 0 W 0 W 0 W 1 -- 1 -- 1 -- 1 -- 7 6 5 4
H'FFB0
3 2 1
Port 1
0
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR 1 -- 0 W 1 -- 0 W 1 -- 0 W 1 -- 0 W
Port 1 Input/Output Control 0 Input port 1 Output port
P1DR--Port 1 Data Register
Bit Initial value Read/Write 7 P17 0 R/W 6 P16 0 R/W 5 P15 0 R/W 4 P14 0 R/W
H'FFB2
3 P13 0 R/W 2 P12 0 R/W 1 P11 0 R/W
Port 1
0 P10 0 R/W
490
P2DDR--Port 2 Data Direction Register
Bit Mode 1 Initial value Read/Write Modes 2 and 3 Initial value Read/Write 0 W 0 W 0 W 0 W 1 -- 1 -- 1 -- 1 -- 7 6 5 4
H'FFB1
3 2 1
Port 2
0
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR 1 -- 0 W 1 -- 0 W 1 -- 0 W 1 -- 0 W
Port 2 Input/Output Control 0 Input port 1 Output port
P2DR--Port 2 Data Register
Bit Initial value Read/Write 7 P27 0 R/W 6 P26 0 R/W 5 P25 0 R/W 4 P24 0 R/W
H'FFB3
3 P23 0 R/W 2 P22 0 R/W 1 P21 0 R/W
Port 2
0 P20 0 R/W
P3DDR--Port 3 Data Direction Register
Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W
H'FFB4
3 0 W 2 0 W 1 0 W
Port 3
0 0 W
P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR
Port 3 Input/Output Control 0 Input port 1 Output port
491
P3DR--Port 3 Data Register
Bit Initial value Read/Write 7 P37 0 R/W 6 P36 0 R/W 5 P35 0 R/W 4 P34 0 R/W
H'FFB6
3 P33 0 R/W 2 P32 0 R/W 1 P31 0 R/W
Port 3
0 P30 0 R/W
P4DDR--Port 4 Data Direction Register
Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W
H'FFB5
3 0 W 2 0 W 1 0 W
Port 4
0 0 W
P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR
Port 4 Input/Output Control 0 Input port 1 Output port
P4DR--Port 4 Data Register
Bit Initial value Read/Write 7 P47 0 R/W 6 P46 0 R/W 5 P45 0 R/W 4 P44 0 R/W
H'FFB7
3 P43 0 R/W 2 P42 0 R/W 1 P41 0 R/W
Port 4
0 P40 0 R/W
P5DDR--Port 5 Data Direction Register
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 --
H'FFB8
3 -- 1 -- 2 0 W 1 0 W
Port 5
0 0 W
P52DDR P51DDR P50DDR
Port 5 Input/Output Control 0 Input port 1 Output port
492
P5DR--Port 5 Data Register
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 --
H'FFBA
3 -- 1 -- 2 P52 0 R/W 1 P51 0 R/W
Port 5
0 P50 0 R/W
P6DDR--Port 6 Data Direction Register
Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W
H'FFB9
3 0 W 2 0 W 1 0 W
Port 6
0 0 W
P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR
Port 6 Input/Output Control 0 Input port 1 Output port
P6DR--Port 6 Data Register
Bit Initial value Read/Write 7 P67 0 R/W 6 P66 0 R/W 5 P65 0 R/W 4 P64 0 R/W
H'FFBB
3 P63 0 R/W 2 P62 0 R/W 1 P61 0 R/W
Port 6
0 P60 0 R/W
P7DR--Port 7 Data Register
Bit Initial value Read/Write 7 P77 * R 6 P76 * R 5 P75 * R 4 P74 * R
H'FFBE
3 P73 * R 2 P72 * R 1 P71 * R
Port 7
0 P70 * R
Note: * Depends on the levels of pins P77 to P70.
493
P8DDR--Port 8 Data Direction Register
Bit Initial value Read/Write 7 -- 1 -- 6 0 W 5 0 W 4 0 W
H'FFBD
3 0 W 2 0 W 1 0 W
Port 8
0 0 W
P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR
Port 8 Input/Output Control 0 Input port 1 Output port
P8DR--Port 8 Data Register
Bit Initial value Read/Write 7 -- 1 -- 6 P86 0 R/W 5 P85 0 R/W 4 P84 0 R/W
H'FFBF
3 P83 0 R/W 2 P82 0 R/W 1 P81 0 R/W
Port 8
0 P80 0 R/W
P9DDR--Port 9 Data Direction Register
Bit Modes 1 and 2 Initial value Read/Write Mode 3 Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 1 -- 0 W 0 W 7 6 5 4
H'FFC0
3 2 1
Port 9
0
P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
Port 9 Input/Output Control 0 Input port 1 Output port
494
P9DR--Port 9 Data Register
Bit Initial value Read/Write 7 P97 0 R/W 6 P96 * R 5 P95 0 R/W 4 P94 0 R/W
H'FFC1
3 P93 0 R/W 2 P92 0 R/W 1 P91 0 R/W
Port 9
0 P90 0 R/W
Note: * Depends on the level of pin P96.
WSCR--Wait-State Control Register
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 CKDBL 0 R/W 4 -- 1 --
H'FFC2
3 WMS1 0 R/W 2 WMS0 0 R/W 1 WC1 0 R/W 0 WC0 0 R/W
Wait Count 0 0 No wait states inserted by wait-state controller 0 1 1 state inserted 1 0 2 states inserted 1 1 3 states inserted
Wait Mode Select 0 0 Programmable wait mode 0 1 No wait states inserted by wait-state controller 1 0 Pin wait mode 1 1 Pin auto-wait mode
Clock Double 0 Clock for supporting modules is not divided (oP = o) 1 Clock for supporting modules is divided by 2 (oP = o/2)
495
STCR--Serial/Timer Control Register
Bit Initial value Read/Write 7 RING 0 R/W 6 CMPF 0 R/(W)* 5 CMPIE 0 R/W 4 LOAD 1 (W)
H'FFC3
3 MARK 1 (W) 2 -- 1 -- 1 ICKS1 0 R/W
TMR0/1
0 ICKS0 0 R/W
Internal Clock Source Select See TCR under TMR0 and TMR1. Pointer Mark 0 DTARB contents are copied to RLARB 1 No operation Pointer Load 0 RLARB contents are copied to DTARB 1 No operation Compare Interrupt Enable 0 Interrupt request (CMPI) by CMPF is disabled 1 Interrupt request (CMPI) by CMPF is enabled Compare Interrupt Flag 0 Cleared by reading CMPF = 1, then writing 0 in CMPF 1 Ring buffer overrun error Set when DTARB contents match CPARB contents after being incremented by DTU cycle occurrence Ring Buffer Mode 0 DTU channel B does not operate in ring buffer mode 1 DTU channel B operates in ring buffer mode Note: * Software can write a 0 in bit 6 to clear the flag, but cannot write a 1 in this bit.
496
SYSCR--System Control Register
Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W
H'FFC4
3 XRST 1 R 2 NMIEG 0 R/W 1 DPME 0 R/W 0 RAME 1 R/W
RAM Enable 0 On-chip RAM is disabled. 1 On-chip RAM is enabled. Dual-Port RAM Mode Enable 0 Not being set to slave mode. 1 Being set to slave mode. NMI Edge 0 Falling edge of NMI is detected. 1 Rising edge of NMI is detected. External Reset 0 The chip is reset by a watchdog timer overflow. 1 The chip is reset by an external reset signal. Standby Timer Select 0 0 0 Clock settling time = 8,192 states 0 0 1 Clock settling time = 16,384 states 0 1 0 Clock settling time = 32,768 states 0 1 1 Clock settling time = 65,536 states 1 0 -- Clock settling time = 131,072 states 1 1 -- Prohibited Software Standby 0 SLEEP instruction causes transition to sleep mode. 1 SLEEP instruction causes transition to software standby mode.
497
MDCR--Mode Control Register
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 0 --
H'FFC5
3 -- 0 -- 2 -- 1 -- 1 MDS1 * R 0 MDS0 * R
Mode Select Bits Value at mode pins. Note: * Determined by inputs at pins MD1 and MD0.
ISCR--IRQ Sense Control Register
Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FFC6
3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
IRQ7SC IRQ6SC IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC
IRQ0 to IRQ7 Sense Control 0 IRQ0 to IRQ7 are level-sensed (active low). 1 IRQ0 to IRQ7 are edge-sensed (falling edge).
IER--IRQ Enable Register
Bit Initial value Read/Write 7 IRQ7E 0 R/W 6 IRQ6E 0 R/W 5 IRQ5E 0 R/W 4 IRQ4E 0 R/W
H'FFC7
3 IRQ3E 0 R/W 2 IRQ2E 0 R/W 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W
IRQ0 to IRQ7 Enable 0 IRQ0 to IRQ7 are disabled. 1 IRQ0 to IRQ7 are enabled.
498
TCR--Timer Control Register
Bit Initial value Read/Write 7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W
H'FFC8
3 CCLR0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W
TMR0
0 CKS0 0 R/W
Clock Select TCR 0 0 0 0 0 0 0 1 1 1 1 Counter Clear 0 0 Counter is not cleared. 0 1 Cleared by compare-match A. 1 0 Cleared by compare-match B. 1 1 Cleared on rising edge of external reset input. Timer Overflow Interrupt Enable 0 Overflow interrupt request is disabled. 1 Overflow interrupt request is enabled. Compare-Match Interrupt Enable A 0 Compare-match A interrupt request is disabled. 1 Compare-match A interrupt request is enabled. Compare-Match Interrupt Enable B 0 Compare-match B interrupt request is disabled. 1 Compare-match B interrupt request is enabled. 499 0 0 0 1 1 1 1 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 STCR -- -- -- -- -- -- -- -- -- -- -- -- 0 1 0 1 0 1 -- -- -- -- CKS2 CKS1 CKS0 ICKS1 ICKS0 Description Timer stopped oP/8 internal clock, falling edge oP/2 internal clock, falling edge oP/64 internal clock, falling edge oP/32 internal clock, falling edge oP/1024 internal clock, falling edge oP/256 internal clock, falling edge Timer stopped External clock, rising edge External clock, falling edge External clock, rising and falling edges
TCSR--Timer Control/Status Register
Bit Initial value Read/Write 7 CMFB 0 R/(W) *1 6 CMFA 0 5 OVF 0 4 PWME 0 R/W
H'FFC9
3 OS3 *2 0 R/W 2 OS2 *2 0 R/W 1 OS1*2 0 R/W 0
TMR0
OS0*2 0 R/W
R/(W)*1 R/(W)*1
Output Select 0 0 No change on compare-match A. 0 1 Output 0 on compare-match A. 1 0 Output 1 on compare-match A. 1 1 Invert (toggle) output on compare-match A. Output Select 0 0 No change on compare-match B. 0 1 Output 0 on compare-match B. 1 0 Output 1 on compare-match B. 1 1 Invert (toggle) output on compare-match B. PWM Mode Enable 0 Normal timer mode 1 PWM mode Timer Overflow Flag 0 Cleared by reading OVF = 1, then writing 0 in OVF. 1 Set when TCNT changes from H'FF to H'00. Compare-Match Flag A 0 Cleared by reading CMFA = 1, then writing 0 in CMFA. 1 Set when TCNT = TCORA. Compare-Match Flag B 0 Cleared by reading CMFB = 1, then writing 0 in CMFB. 1 Set when TCNT = TCORB.
Notes: 1. Software can write a 0 in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits. 2. When all four bits (OS3 to OS0) are cleared to 0, output is disabled. 500
TCORA--Time Constant Register A
Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W
H'FFCA
3 1 R/W 2 1 R/W 1 1 R/W
TMR0
0 1 R/W
The CMFA bit is set to 1 when TCORA = TCNT.
TCORB--Time Constant Register B
Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W
H'FFCB
3 1 R/W 2 1 R/W 1 1 R/W
TMR0
0 1 R/W
The CMFB bit is set to 1 when TCORB = TCNT.
TCNT--Timer Counter
Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FFCC
3 0 R/W 2 0 R/W 1 0 R/W
TMR0
0 0 R/W
Count value
501
NDER2--Next Data Enable Register 2
Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FFCD
3 0 R/W 2 0 R/W 1 0 R/W 0 0
TPC
NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 R/W
Next Data Enable 15 to 8 Bits 7 to 0 NDER15 to 8 0 1 Description TPC outputs TP15 to TP8 are disabled (NDR15 to NDR8 cannot be transferred to P27 to P20) TPC outputs TP15 to TP8 are enabled (NDR15 to NDR8 can be transferred to P27 to P20)
502
NDRB--Next Data Register B * Same Trigger for TPC Output Groups 2 and 3 Address H'FFCE
Bit Initial value Read/Write 7 NDR15 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4
H'FFCE/H'FFD6
TPC
3 NDR11 0 R/W
2 NDR10 0 R/W
1 NDR9 0 R/W
0 NDR8 0 R/W
NDR12 0 R/W
Next output data for TPC output group 3
Next output data for TPC output group 2
Address H'FFD6
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
* Different Triggers for TPC Output Groups 2 and 3 Address H'FFCE
Bit Initial value Read/Write 7 NDR15 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
Next output data for TPC output group 3
Address H'FFD6
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W
Next output data for TPC output group 2 503
NDRA--Next Data Register A * Same Trigger for TPC Output Groups 0 and 1 Address H'FFCF
Bit Initial value Read/Write 7 NDR7 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W
H'FFCF/H'FFD7
TPC
3 NDR3 0 R/W
2 NDR2 0 R/W
1 NDR1 0 R/W
0 NDR0 0 R/W
Next output data for TPC output group 1
Next output data for TPC output group 0
Address H'FFD7
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
* Different Triggers for TPC Output Groups 0 and 1 Address H'FFCF
Bit Initial value Read/Write 7 NDR7 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
Next output data for TPC output group 1
Address H'FFD7
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W
Next output data for TPC output group 0
504
TCR--Timer Control Register
Bit Initial value Read/Write 7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W
H'FFD0
3 CCLR0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W
TMR1
0 CKS0 0 R/W
Clock Select TCR 0 0 0 0 0 0 0 1 1 1 1 Counter Clear 0 0 Counter is not cleared. 0 1 Cleared by compare-match A. 1 0 Cleared by compare-match B. 1 1 Cleared on rising edge of external reset input. Timer Overflow Interrupt Enable 0 Overflow interrupt request is disabled. 1 Overflow interrupt request is enabled. Compare-Match Interrupt Enable A 0 Compare-match A interrupt request is disabled. 1 Compare-match A interrupt request is enabled. Compare-Match Interrupt Enable B 0 Compare-match B interrupt request is disabled. 1 Compare-match B interrupt request is enabled. 505 0 0 0 1 1 1 1 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 STCR -- 0 1 0 1 0 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CKS2 CKS1 CKS0 ICKS1 ICKS0 Description Timer stopped oP/8 internal clock, falling edge oP/2 internal clock, falling edge oP/64 internal clock, falling edge oP/128 internal clock, falling edge oP/1024 internal clock, falling edge oP/2048 internal clock, falling edge Timer stopped External clock, rising edge External clock, falling edge External clock, rising and falling edges
TCSR--Timer Control/Status Register
Bit Initial value Read/Write 7 CMFB 0 R/(W) *1 6 CMFA 0 5 OVF 0 4 PWME 0 R/W
H'FFD1
3 OS3*2 0 R/W 2 OS2 *2 0 R/W 1 OS1*2 0 R/W 0
TMR1
OS0*2 0 R/W
R/(W) *1 R/(W) *1
Notes: Bit functions are the same as for TMR0. 1. Software can write a 0 in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits. 2. When all four bits (OS3 to OS0) are cleared to 0, output is disabled.
TCORA--Time Constant Register A
Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W
H'FFD2
3 1 R/W 2 1 R/W 1 1 R/W
TMR1
0 1 R/W
Note: Bit functions are the same as for TMR0.
TCORB--Time Constant Register B
Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W
H'FFD3
3 1 R/W 2 1 R/W 1 1 R/W
TMR1
0 1 R/W
Note: Bit functions are the same as for TMR0.
TCNT--Timer Counter
Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FFD4
3 0 R/W 2 0 R/W 1 0 R/W
TMR1
0 0 R/W
Note: Bit functions are the same as for TMR0.
506
NDER1--Next Data Enable Register 1
Bit Initial value Read/Write 7 NDER7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FFD5
3 0 R/W 2 NDER2 0 R/W 1 0 R/W 0 0
TPC
NDER6 NDER5
NDER4 NDER3
NDER1 NDER0 R/W
Next Data Enable 7 to 0 Bits 7 to 0 NDER7 to 0 0 1 Description TPC outputs TP7 to TP0 are disabled (NDR7 to NDR0 cannot be transferred to P17 to P10) TPC outputs TP7 to TP0 are enabled (NDR7 to NDR0 can be transferred to P17 to P10)
507
SMR--Serial Mode Register
Bit Initial value Read/Write 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W
H'FFD8
3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
SCI0
Clock Select 0 0 o clock 0 1 oP/4 clock 1 0 oP/16 clock 1 1 oP/64 clock Multiprocessor Mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Stop Bit Length 0 One stop bit 1 Two stop bits Parity Mode 0 Even parity 1 Odd parity Parity Enable 0 Transmit: No parity bit added. Receive: Parity bit not checked. 1 Transmit: Parity bit added. Receive: Parity bit checked.
Character Length 0 8-bit data length 1 7-bit data length Communication Mode 0 Asynchronous 1 Synchronous
Note: Bit functions are the same as for SCI1. 508
BRR--Bit Rate Register
Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W
H'FFD9
3 1 R/W 2 1 R/W 1 1 R/W 0 1
SCI0
R/W
Constant that determines the bit rate Note: Bit functions are the same as for SCI1.
509
SCR--Serial Control Register
Bit Initial value Read/Write 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W
H'FFDA
3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0
SCI0
CKE0 0 R/W
Clock Enable 0 0 The SCK pin is not used by the SCI. 1 The SCK pin is used for serial clock output. Clock Enable 1 0 Internal clock 1 External clock Transmit End Interrupt Enable 0 TSR-empty interrupt request is disabled. 1 TSR-empty interrupt request is enabled. Multiprocessor Interrupt Enable 0 Multiprocessor receive interrupt function is disabled. 1 Multiprocessor receive interrupt function is enabled. Receive Enable 0 Receive disabled 1 Receive enabled Transmit Enable 0 Transmit disabled 1 Transmit enabled Receive Interrupt Enable 0 Receive interrupt and receive error interrupt requests are disabled. 1 Receive interrupt and receive error interrupt requests are enabled. Transmit Interrupt Enable 0 TDR-empty interrupt request is disabled. 1 TDR-empty interrupt request is enabled. Note: Bit functions are the same as for SCI1.
510
TDR--Transmit Data Register
Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W
H'FFDB
3 1 R/W 2 1 R/W 1 1 R/W 0 1
SCI0
R/W
Transmit data
Note: Bit functions are the same as for SCI1.
511
SSR--Serial Status Register
Bit Initial value Read/Write 7 TDRE 1 R/(W) * 6 RDRF 0 R/(W) * 5 ORER 0 R/(W) * 4 FER 0 R/(W) *
H'FFDC
3 PER 0 R/(W) * 2 TEND 1 R 1 MPB 0 R 0
SCI0
MPBT 0 R/W
Multiprocessor Bit Transfer 0 Multiprocessor bit = 0 in transmit data. 1 Multiprocessor bit = 1 in transmit data. Multiprocessor Bit 0 Multiprocessor bit = 0 in receive data. 1 Multiprocessor bit = 1 in receive data. Transmit End 0 Cleared by reading TDRE = 1, then writing 0 in TDRE. 1 Set to 1 when TE = 0, or when TDRE = 1 at the end of character transmission. Parity Error 0 Cleared by reading PER = 1, then writing 0 in PER. 1 Set when a parity error occurs (parity of receive data does not match parity selected by O/E bit in SMR). Framing Error 0 Cleared by reading FER = 1, then writing 0 in FER. 1 Set when a framing error occurs (stop bit is 0). Overrun Error 0 Cleared by reading ORER = 1, then writing 0 in ORER. 1 Set when an overrun error occurs (next data is completely received while RDRF bit is set to 1). Receive Data Register Full 0 Cleared by reading RDRF = 1, then writing 0 in RDRF. 1 Set when one character is received normally and transferred from RSR to RDR. Transmit Data Register Empty 0 Cleared by reading TDRE = 1, then writing 0 in TDRE. 1 Set when: 1. Data is transferred from TDR to TSR. 2. TE is cleared while TDRE = 0. Note: * Software can write a 0 in bits 7 to 3 to clear the flags, but cannot write a 1 in these bits. Bit functions are the same as for SCI1.
512
RDR--Receive Data Register
Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R
H'FFDD
3 0 R 2 0 R 1 0 R 0 0 R
SCI0
Receive data
Note: Bit functions are the same as for SCI1.
SCMR--Serial Communication Mode Register
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 --
H'FFDE
3 SDIR 0 R/W 2 SINV 0 R/W 1 -- 1 -- 0
SCI0
SMIF 0 R/W
Serial Communication Mode Select 0 Normal SCI mode 1 Reserved mode
Data Invert 0 TDR contents are transmitted as they are. Receive data is stored in RDR as it is. 1 TDR contents are inverted before being transmitted. Receive data is stored in RDR in inverted form.
Data Transfer Direction 0 TDR contents are transmitted LSB-first. Receive data is stored in RDR LSB-first 1 TDR contents are transmitted MSB-first. Receive data is stored in RDR MSB-first.
513
ADDRA (H and L)--A/D Data Register A
Bit Initial value Read/Write
15 14 13 12 11 10 9 8
H'FFE0, H'FFE1
7 6 5 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R
A/D
0 -- 0 R
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
ADDRAH
ADDRAL
A/D Conversion Data 10-bit data giving an A/D conversion result
Reserved Bits
ADDRB (H and L)--A/D Data Register B
Bit Initial value Read/Write
15 14 13 12 11 10 9 8
H'FFE2, H'FFE3
7 6 5 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R
A/D
0 -- 0 R
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
ADDRBH
ADDRBL
A/D Conversion Data 10-bit data giving an A/D conversion result
Reserved Bits
514
ADDRC (H and L)--A/D Data Register C
Bit Initial value Read/Write
15 14 13 12 11 10 9 8
H'FFE4, H'FFE5
7 6 5 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R
A/D
0 -- 0 R
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
ADDRCH
ADDRCL
A/D Conversion Data 10-bit data giving an A/D conversion result
Reserved Bits
ADDRD (H and L)--A/D Data Register D
Bit Initial value Read/Write
15 14 13 12 11 10 9 8
H'FFE6, H'FFE7
7 6 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R
A/D
0 -- 0 R
AD9 AD8 0 R 0 R
AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
ADDRDH
ADDRDL
A/D Conversion Data 10-bit data giving an A/D conversion result
Reserved Bits
515
ADCSR--A/D Control/Status Register
Bit Initial value Read/Write 7 ADF 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W
H'FFE8
3 CKS 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W
A/D
Channel Select Group Selection CH2 0
Channel Selection CH1 0 1 CH0 0 1 0 1 0 1 0 1
Description Single Mode AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Scan Mode AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4 to AN5 AN4 to AN6 AN4 to AN7
1
0 1
Clock Select 0 Conversion time = 266 states (max) 1 Conversion time = 134 states (max) Scan Mode 0 Single mode 1 Scan mode A/D Start 0 A/D conversion is stopped 1 1. Single mode: A/D conversion starts; ADST is automatically cleared to 0 when conversion ends 2. Scan mode: A/D conversion starts and continues, cycling among the selected channels, until ADST is cleared to 0 by software, by a reset, or by a transition to standby mode A/D Interrupt Enable 0 A/D end interrupt request is disabled 1 A/D end interrupt request is enabled A/D End Flag 0 Cleared by reading ADF = 1, then writing 0 in ADF 1 Set when A/D conversion ends in single mode. Set when A/D conversion ends on all selected channels in scan mode. Note: * Only 0 can be written, to clear the flag.
516
ADCR--A/D Control Register
Bit Initial value Read/Write 7 TRGE 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 --
H'FFE9
3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
A/D
Trigger Enable 0 A/D conversion cannot be externally triggered 1 A/D conversion starts at the fall of the external trigger signal (ADTRG)
517
TPMR--TPC Output Mode Register
Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 --
H'FFEA
3 0 R/W 2 0 R/W 1 0 R/W 0 0
TPC
G3NOV G2NOV
G1NOV G0NOV R/W
Group 0 Non-Overlap 0 Normal operation in TPC group 0, output values changing at selected FRT compare match 1 Non-overlapping operation in TPC group 0, using selected FRT compare match A and B Group 1 Non-Overlap 0 Normal operation in TPC group 1, output values changing at selected FRT compare match 1 Non-overlapping operation in TPC group 1, using selected FRT compare match A and B Group 2 Non-Overlap 0 Normal operation in TPC group 2, output values changing at selected FRT compare match 1 Non-overlapping operation in TPC group 2, using selected FRT compare match A and B Group 3 Non-Overlap 0 Normal operation in TPC group 3, output values changing at selected FRT compare match 1 Non-overlapping operation in TPC group 3, using selected FRT compare match A and B
518
TPCR--TPC Output Control Register
Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W
H'FFEB
3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W
TPC
G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0
Group 0 Compare Match Select 1 and 0 Bit 1 G0CMS1 0 Bit 0 G0CMS0 0 1 1 0 1 Output Trigger Selection TPC output group 0 (TP3 to TP0) is triggered by compare match A in FRT1 TPC output group 0 (TP3 to TP0) is triggered by compare match A in FRT0 TPC output group 0 (TP3 to TP0) is triggered by compare match B in FRT1 (and can be non-overlapped) TPC output group 0 (TP3 to TP0) is triggered by compare match B in FRT0 (and can be non-overlapped)
Group 1 Compare Match Select 1 and 0 Bit 3 G1CMS1 0 Bit 2 G1CMS0 0 1 1 0 1 Output Trigger Selection TPC output group 1 (TP7 to TP4) is triggered by compare match A in FRT1 TPC output group 1 (TP7 to TP4) is triggered by compare match A in FRT0 TPC output group 1 (TP7 to TP4) is triggered by compare match B in FRT1 (and can be non-overlapped) TPC output group 1 (TP7 to TP4) is triggered by compare match B in FRT0 (and can be non-overlapped)
Group 2 Compare Match Select 1 and 0 Bit 5 G2CMS1 0 Bit 4 G2CMS0 0 1 1 0 1 Output Trigger Selection TPC output group 2 (TP11 to TP8) is triggered by compare match A in FRT1 TPC output group 2 (TP11 to TP8) is triggered by compare match A in FRT0 TPC output group 2 (TP11 to TP8) is triggered by compare match B in FRT1 (and can be non-overlapped) TPC output group 2 (TP11 to TP8) is triggered by compare match B in FRT0 (and can be non-overlapped)
Group 3 Compare Match Select 1 and 0 Bit 7 G3CMS1 0 Bit 6 G3CMS0 0 1 1 0 1 Output Trigger Selection TPC output group 3 (TP15 to TP12) is triggered by compare match A in FRT1 TPC output group 3 (TP15 to TP12) is triggered by compare match A in FRT0 TPC output group 3 (TP15 to TP12) is triggered by compare match B in FRT1 (and can be non-overlapped) TPC output group 3 (TP15 to TP12) is triggered by compare match B in FRT0 (and can be non-overlapped)
519
PCCSR--Parallel Communication Control/Status Register H'FFF0 (000*1 from Master) DTU
Bit Initial value Read/Write Internal CPU Master CPU R R R R/W R R/W R R/W R/(W) R R/(W) R R/W R R/W R 7 QREF 0 6 0 5 0 4 0 3 0 2 MREF 1 1 EMWI 0 0 EMRI 0
EWRQ EWAKAR ERAKAR MWEF
Enable Master Read Interrupt 0 Disables interrupt request (MREI) by MREF 1 Enables interrupt request (MREI) by MREF Enable Master Write Interrupt 0 Disables interrupt request (MWEI) by MWEF 1 Enables interrupt request (MWEI) by MWEF Master Read End Flag*2 Master Write End Flag*2 Enable Write Acknowledge and Request*2 (Enables operation of the RDY pin by master write access) Enable Read Acknowledge and Request*2 (Enables operation of the RDY pin by master read access) Enable Wait Request*2 (Enables operation of the WRQ pin) Query Read End Flag 0 DPDRRQ contains data Cleared when DTC writes on-chip RAM data in DPDRRQ 1 DPDRRQ contains the lower byte of an on-chip RAM address Set when master CPU writes lower byte of an on-chip RAM address in DPDRRQ Notes: 1. Value of register select inputs (RS2 to RS0) by which the master CPU selects a PBI register. 2. For details see section 5, DTU.
520
DPDRRQ--DPRAM Data Register Query Read
Bit Initial value Read/Write Internal CPU Master CPU W* R/W W* R/W W* R/W W* R/W 7 -- 6 -- 5 -- 4 --
-- (001 from Master)
3 -- W* R/W 2 -- W* R/W 1 -- W* R/W 0 --
DTU
W* R/W
On-chip RAM data, or lower 8 bits of on-chip RAM address Note: * Transferred automatically from on-chip RAM by DTU.
RLARA--Reload Address Register A
Bit Initial value Read/Write 7 -- R/W 6 -- R/W 5 -- R/W 4 -- R/W
H'FFF2 (-- from Master)
3 -- R/W 2 -- R/W 1 -- R/W 0 --
DTU
R/W
Data for initializing DTAR at boundary overflow
RLARB--Reload Address Register B
Bit Initial value Read/Write 7 -- R/W 6 -- R/W 5 -- R/W 4 -- R/W
H'FFF3 (-- from Master)
3 -- R/W 2 -- R/W 1 -- R/W 0 --
DTU
R/W
Data for initializing DTAR at boundary overflow, and auxiliary pointer in ring-buffer mode
521
CPARB--Compare Address Register B
Bit Initial value Read/Write 7 -- R/W 6 -- R/W 5 -- R/W 4 -- R/W
H'FFF4 (-- from Master)
3 -- R/W 2 -- R/W 1 -- R/W 0 --
DTU
R/W
Auxiliary pointer in ring-buffer mode
DTARH--Data Transfer Address Register H
Bit Initial value Read/Write 7 -- R/W 6 -- R/W 5 -- R/W 4 -- R/W
H'FFF5 (-- from Master)
3 -- R/W 2 -- R/W 1 -- R/W 0 --
DTU
R/W
Upper 8 bits of on-chip RAM address
522
IOCR--I/O Control Register
Bit Initial value Read/Write 7 HSCE 0 R/W 6 DPEA 0 R/W 5 DPEB 0 R/W 4 RPEA 0 R/W
H'FFF1 (-- from Master)
3 RPEB 0 R/W 2 RPEC 0 R/W 1 -- 1 -- 0 -- 1 --
DTU
Repeat Enable 0 Transfer in normal mode 1 Transfer in repeat mode DPRAM Enable 0 I/O transfer or direct word mode 1 Bound buffer mode Parallel Handshake Enable 0 Handshake mode 1 DPRAM mode Note: The DPME, HSCE, DPEA, and DPEB bits combine to specify the following modes. DTC Operating Mode Settings
DPME 1 Hand- Query Buffer Bound Buffer Bound Buffer Direct Word Bit 7 Bit 6 Bit 5 shake Operation Mode Mode Mode HSCE DPEA DPEB Mode (DTC Channel R) (DTC Channel A) (DTC Channel B) (DPDRRH/L) 1 0 -- 0 1 0 1 0 -- -- -- 0 0 1 1 -- x x x x x x x (read) (read) (read) (read) I/O transfer I/O transfer (read) I/O transfer (read) I/O transfer I/O transfer I/O transfer I/O transfer (write) (write) I/O transfer x Handshake (read) Bound buffer (read) Bound buffer Direct Word Mode (DPDRWH/L) Handshake (write) (write) Bound buffer Bound buffer x
Note: For I/O transfer, set the DTE bit to 1 in DTCRA, DTCRB, or DTCRC. Handshake mode operation is only supported in single-chip mode. Do not set bit HSCE to 1 in expanded mode.
523
DTCRA--Data Transfer Control Register A
Bit Initial value Read/Write I/O transfer Bound buffer Internal CPU Master CPU 0 0 R/W R R/W R R/W R R/W R/W R/W R/W 7 DTE 0 6 DTIE 0 5 BUD2 0 4 BUD1 0
H'FFF6 (010 from Master)
3 BUD0 0 R/W R/W R 2 SOS2 0 R/W R/W R 1 SOS1 0 R/W R/W R
DTU
0 SOS0 0 R/W R/W R
Source Select SOS2 SOS1 SOS0 Interrupt Source RXI0 0 0 1 TXI0 0 1 0 ADI 0 1 1 OCIA1 1 0 0 OCIA1 1 0 1 OCIB1 1 1 0 -- 1 1 1 Boundary BUD2 BUD1 BUD0 DTAR Overflow Timing End of each byte transfer 0 0 0 Carry from bit 0 to bit 1 0 0 1 Carry from bit 1 to bit 2 0 1 0 Carry from bit 2 to bit 3 0 1 1 Carry from bit 3 to bit 4 1 0 0 Carry from bit 4 to bit 5 1 0 1 Carry from bit 5 to bit 6 1 1 0 Carry from bit 6 to bit 7 1 1 1 Data Transfer Interrupt Enable 0 Disables the interrupt requested when the DTE bit is cleared to 0 (DTIA) 1 Enables the interrupt requested when the DTE bit is cleared to 0 (DTIA) Data Transfer Enable 0 1 Indicates that I/O transfer is halted Cleared when 0 is written in DTE, or when a transfer terminates at the boundary in normal mode Indicates that I/O transfer is in progress Set by reading DTCR while DTE = 0, then writing 1 in DTE Max. Bytes Transferred 1 2 4 8 16 32 64 128 Module SCI0 SCI0 ADC FRT1 FRT1 FRT1 -- Clearing of Source Transfer RDR RAM (byte) RAM TDR (byte) ADDRA RAM (word) RAM OCRA (word) RAM OCRA (word) x RAM OCRB (word) x Reserved --
Note: 0: Always read as 0.
524
DTARA--Data Transfer Address Register A
Bit Initial value Read/Write I/O transfer Bound buffer Internal CPU Master CPU R/W R R/W R R/W R R/W R R/W R/W R/W R/W 7 -- 6 -- 5 -- 4 --
H'FFF7 (011 from Master)
3 -- R/W R/W R 2 -- R/W R/W R 1 -- R/W R/W R 0 --
DTU
R/W R/W R
Lower 8 bits of on-chip RAM address
525
DTCRB--Data Transfer Control Register B
Bit Initial value Read/Write I/O transfer Bound buffer Internal CPU Master CPU 0 -- 0 -- R W R W R/W R/W R/W R/W 7 DTE 0 6 DTIE 0 5 BUD2 0 4 BUD1 0
H'FFF8 (010 from Master)
3 BUD0 0 R/W R W 2 SOS2 0 R/W 0 -- 1 SOS1 0 R/W 0 -- 0
DTU
SOS0 0 R/W 0 --
Source Select SOS2 SOS1 SOS0 Interrupt Source RXI0 0 0 1 TXI0 0 1 0 ADI 0 1 1 OCIA1 1 0 0 OCIA1 1 0 1 OCIA1 1 1 0 OCIA1 1 1 1 Boundary BUD2 BUD1 BUD0 DTAR Overflow Timing End of each byte transfer 0 0 0 Carry from bit 0 to bit 1 0 1 0 Carry from bit 1 to bit 2 1 0 0 Carry from bit 2 to bit 3 1 1 0 Carry from bit 3 to bit 4 0 0 1 Carry from bit 4 to bit 5 0 1 1 Carry from bit 5 to bit 6 1 0 1 Carry from bit 6 to bit 7 1 1 1 Data Transfer Interrupt Enable 0 Disables the interrupt requested when the DTE bit is cleared to 0 (DTIB) 1 Enables the interrupt requested when the DTE bit is cleared to 0 (DTIB) Data Transfer Enable 0 1 Indicates that I/O transfer is halted Cleared when 0 is written in DTE, or when a transfer terminates at the boundary in normal mode Indicates that I/O transfer is in progress Set by reading DTCR while DTE = 0, then writing 1 in DTE Max. Bytes Transferred 1 2 4 8 16 32 64 128 Module SCI0 SCI0 ADC TPC TPC FRT1 FRT1 Clearing of Source Transfer RDR RAM (byte) RAM TDR (byte) ADDRA RAM (word) RAM NDRB (word) RAM NDRA (byte) RAM OCRA (word) RAM OCRA (word) x
Notes: -- : Cannot be used. Cannot be modified. 0 : Always read as 0.
526
DTARB--Data Transfer Address Register B
Bit Initial value Read/Write I/O transfer Bound buffer Internal CPU Master CPU R W R W R W R W R/W R/W R/W R/W 7 -- 6 -- 5 -- 4 --
H'FFF9 (011 from Master)
3 -- R/W R W 2 -- R/W R W 1 -- R/W R W 0 --
DTU
R/W R W
Lower 8 bits of on-chip RAM address
527
DTCRC--Data Transfer Control Register C
Bit Initial value Read/Write 7 DTE 0 R/W 6 DTIE 0 R/W 5 BUD2 0 R/W 4 BUD1 0 R/W
H'FFFA (-- from Master)
3 BUD0 0 R/W 2 SOS2 0 R/W 1 SOS1 0 R/W 0
DTU
SOS0 0 R/W
Source Select SOS2 SOS1 SOS0 Interrupt Source RXI0 0 0 1 TXI0 0 1 0 ADI 0 1 1 OCIB1 1 0 0 OCIA1 1 0 1 OCIB1 1 1 0 OCIA1 1 1 1 Boundary BUD2 BUD1 BUD0 DTAR Overflow Timing End of each byte transfer 0 0 0 Carry from bit 0 to bit 1 0 0 1 Carry from bit 1 to bit 2 0 1 0 Carry from bit 2 to bit 3 0 1 1 Carry from bit 3 to bit 4 1 0 0 Carry from bit 4 to bit 5 1 0 1 Carry from bit 5 to bit 6 1 1 0 Carry from bit 6 to bit 7 1 1 1 Data Transfer Interrupt Enable 0 Disables the interrupt requested when the DTE bit is cleared to 0 (DTIC) 1 Enables the interrupt requested when the DTE bit is cleared to 0 (DTIC) Data Transfer Enable 0 1 Indicates that I/O transfer is halted Cleared when 0 is written in DTE, or when a transfer terminates at the boundary in normal mode Indicates that I/O transfer is in progress Set by reading DTCR while DTE = 0, then writing 1 in DTE Max. Bytes Transferred 1 2 4 8 16 32 64 128 Module SCI0 SCI0 ADC TPC TPC TPC TPC Clearing of Source Transfer RDR RAM (byte) RAM TDR (byte) ADDRA RAM (word) RAM NDRB (word) RAM NDRB (word) RAM NDRA (byte) RAM NDRA (byte)
528
DTARC--Data Transfer Address Register C
Bit Initial value Read/Write 7 -- R/W 6 -- R/W 5 -- R/W 4 -- R/W
H'FFFB (-- from Master)
3 -- R/W 2 -- R/W 1 -- R/W 0 --
DTU
R/W
Lower 8 bits of on-chip RAM address
DPDRWH--DPRAM Data Register Write H
Bit Initial value Read/Write Bound buffer mode On-chip CPU Master CPU Direct word mode Internal CPU Master CPU R W R W R W R W R* W R* W R* W R* W 7 -- 6 -- 5 -- 4 --
H'FFFC (100 from Master)
3 -- 2 -- 1 --
DTU
0 --
R* W R W
R* W R W
R* W R W
R* W R W
Data register reserved for write access by master CPU. Note: * Transferred to on-chip RAM automatically by the DTU.
529
DPDRWL--DPRAM Data Register Write L
Bit Initial value Read/Write Bound buffer mode On-chip CPU Master CPU Direct word mode Internal CPU Master CPU Handshake mode Internal CPU Master CPU R W *2 R W *2 R W *2 R W *2 R W R W R W R W R *1 W R *1 W R*1 W R *1 W 7 -- 6 -- 5 -- 4 --
H'FFFD (101 from Master)
3 -- 2 -- 1 --
DTU
0 --
R *1 W R W R W *2
R*1 W R W R W *2
R *1 W R W R W *2
R *1 W R W R W *2
Data register reserved for write access by master CPU. Notes: 1. Transferred to on-chip RAM automatically by the DTU. 2. Data on the DDB lines is latched at the falling edge of the WE input.
DPDRRH--DPRAM Data Register Read H
Bit Initial value Read/Write Bound buffer mode On-chip CPU Master CPU Direct word mode Internal CPU Master CPU W R W R W R W R W* R W* R W* R W* R 7 -- 6 -- 5 -- 4 --
H'FFFE (110 from Master)
3 -- 2 -- 1 --
DTU
0 --
W* R W R
W* R W R
W* R W R
W* R W R
Data register reserved for read access by the master CPU. Note: * Transferred from on-chip RAM automatically by the DTU.
530
DPDRRL--DPRAM Data Register Read L
Bit Initial value Read/Write Bound buffer mode On-chip CPU Master CPU Direct word mode Internal CPU Master CPU Handshake mode Internal CPU Master CPU W R *2 W R *2 W R *2 W R *2 W R W R W R W R W *1 R W *1 R W *1 R W *1 R 7 -- 6 -- 5 -- 4 --
H'FFFF (111 from Master)
3 -- 2 -- 1 --
DTU
0 --
W *1 R W R W R *2
W *1 R W R W R *2
W *1 R W R W R *2
W *1 R W R W R*2
Data register reserved for read access by the master CPU. Notes: 1. Transferred from on-chip RAM automatically by the DTU. 2. Data is output on the DDB lines when the OE input is low.
531
Appendix C I/O Port Block Diagrams
C.1 Port 1 Block Diagram
Reset Internal lower address bus TPC Next data WP1D Output trigger Output enable Mode 1 Mode 2 R Q D P1nPCR C RP1P WP1P
Hardware standby
Mode 1
Reset
SR* Q D P1nDD C Mode 3 WP1D Reset P1n R Q D P1nDR C
RP1
WP1P: Write to P1PCR WP1D: Write to P1DDR WP1: Write to port 1 RP1P: Read P1PCR RP1: Read port 1 n = 0 to 7 Note: * Set priority
Figure C.1 Port 1 Block Diagram
532
Internal data bus
C.2
Port 2 Block Diagram
Reset Internal upper address bus TPC Next data WP2D Output trigger Output enable Mode 1 Mode 2 R Q D P2nPCR C RP2P WP2P
Hardware standby
Mode 1
Reset SR* Q D P2nDD C WP2D Reset
Mode 3
P2n
R Q D P2nDR C
RP2
WP2P: Write to P2PCR WP2D: Write to P2DDR WP2: Write to port 2 RP2P: Read P2PCR RP2: Read port 2 n = 0 to 7 Note: * Set priority
Figure C.2 Port 2 Block Diagram
Internal data bus
533
C.3
Port 3 Block Diagram
DPME Mode 3 Mode 3 Reset R Q D P3nPCR C RP3P CS OE WP3P Reset R Q D P3nDDR C WP3D Reset P3n R Q D P3nDR C WP3 Modes 1 and 2 CS WE DPRAM data bus Internal data bus
External address write
External address read
RP3
WP3P: Write to P3PCR WP3D: Write to P3DDR WP3: Write to port 3 RP3P: Read P3PCR RP3: Read port 3 n = 0 to 7 Note: When HSCE = 1, CS is internally fixed to 0.
Figure C.3 Port 3 Block Diagram
534
C.4
Port 4 Block Diagrams
DPRAM data bus DPME Modes 1 and 2
OE CS
Reset R Q D P4nDDR C WP4D
P4n
CS WE
Reset R Q D P4nDR C WP4
RP4
8-bit timer input bus WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 n = 0, 2, 3, 5 Note: When HSCE = 1, CS is internally fixed to 0.
8-bit timer Counter clock input Counter reset input
Figure C.4 (a) Port 4 Block Diagram (Pins P4 0, P42, P43, P45)
Internal data bus
535
DPME Modes 1 and 2 DPRAM data bus 8-bit timer Free-running timer Output enable 8-bit timer output Output compare output Internal data bus
OE CS
Reset R Q D P4nDDR C WP4D Reset R Q D P4nDR C WP4 CS WE
P4n
RP4
WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 n = 1, 4, 6, 7 Note: When HSCE = 1, CS is internally fixed to 0.
Figure C.4 (b) Port 4 Block Diagram (Pins P41, P44, P46, P47)
536
C.5
Port 5 Block Diagrams
Reset Internal data bus SCI Output enable Serial transmit data R Q D P50DDR C WP5D
Reset P50 R Q D P50DR C WP5
RP5
WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5
Figure C.5 (a) Port 5 Block Diagram (Pin P5 0)
537
Reset R Q D P51DDR C WP5D Reset P51 R Q D P51DR C WP5
Internal data bus SCI Input enable Serial receive data
RP5
WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5
Figure C.5 (b) Port 5 Block Diagram (Pin P51)
538
Reset R Q D P52DDR C WP5D Reset P52 R Q D P52DR C WP5
Internal data bus SCI Clock input enable Clock output enable Clock output Clock input
RP5
WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5
Figure C.5 (c) Port 5 Block Diagram (Pin P52)
539
C.6
Port 6 Block Diagrams
Reset R Q D P6nDDR C WP6D
Reset P6n R Q D P6nDR C WP6
RP6
Free-running timer Input capture input DPME Modes 1 and 2 Counter clock input
WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 n = 0, 3, 5
8-bit timer input bus
Figure C.6 (a) Port 6 Block Diagram (Pins P6 0, P63, P65)
540
Internal data bus
R Q D P61DDR C WP6D Reset P61 R Q D P61DR C WP6
Internal data bus Free-running timer Output enable Output compare output
Reset
RP6
WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6
Figure C.6 (b) Port 6 Block Diagram (Pin P61)
541
R Q D P62DDR C WP6D Reset P62 R Q D P62DR C WP6
RP6
Internal data bus Free-running timer Input capture input
Reset
WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6
Figure C.6 (c) Port 6 Block Diagram (Pin P62)
542
R Q D P64DDR C WP6D Reset P64 R Q D P64DR C Modes 1 and 2 DPME WP6
Internal data bus 8-bit timer Output enable 8-bit timer output Free-running timer Input capture input
Reset
RP6
WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6
Figure C.6 (d) Port 6 Block Diagram (Pin P64)
543
R Q D P66DDR C WP6D Reset P66 R Q D P66DR C WP6
Internal data bus Free-running timer Output enable Output compare output 8-bit timer input bus (TMRI1) IRQ6 input IRQ enable register IRQ6 enable
Reset
RP6
DPME Modes 1 and 2
WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6
Figure C.6 (e) Port 6 Block Diagram (Pin P66)
544
R Q D P67DDR C WP6D Reset P67 R Q D P67DR C Modes 1 and 2 DPME WP6
Internal data bus 8-bit timer Output enable 8-bit timer output IRQ7 input IRQ enable register IRQ7 enable
Reset
RP6
WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6
Figure C.6 (f) Port 6 Block Diagram (Pin P67)
545
C.7
Port 7 Block Diagram
RP7 P7n
Internal data bus A/D converter Analog input
RP7: Read port 7 n = 0 to 7
Figure C.7 Port 7 Block Diagram (Pins P70 to P77)
546
C.8
Port 8 Block Diagrams
DPME HSCE Reset Internal data bus PBI Register select input R Q D P8nDDR C WP8D Reset P8n R Q D P8nDR C WP8
RP8
WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 n = 0 to 2
Figure C.8 (a) Port 8 Block Diagram (Pins P8 0 to P82)
547
DPME
Internal data bus
Reset R Q D P83DDR C WP8D
PBI
WRQ output enable WRQ signal P83 Modes 1 and 2 Reset R Q D P83DR C WP8
RDY signal
RP8
WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8
Figure C.8 (b) Port 8 Block Diagram (Pin P83)
548
Reset R Q D P84DDR C WP8D Reset P84 R Q D P84DR C WP8 Output enable Serial transmit data Internal data bus SCI IRQ3 input IRQ enable register IRQ3 enable WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 DPME Modes 1 and 2 PBI input bus (WE)
RP8
Figure C.8 (c) Port 8 Block Diagram (Pin P84)
549
Reset R Q D P85DDR C WP8D
Internal data bus
SCI Input enable Serial receive data IRQ4 input IRQ enable register IRQ4 enable
Reset P85 R Q D P85DR C WP8
RP8
WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8
Figure C.8 (d) Port 8 Block Diagram (Pin P85)
550
Reset Q C WP8D R D
P86DDR
Internal data bus
SCI Clock input enable Clock output enable Clock output Clock input IRQ5 input IRQ enable register IRQ5 enable PBI input bus (OE)
Reset P86 R Q D P86DR C WP8
RP8
WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8
DPME Modes 1 and 2
Figure C.8 (e) Port 8 Block Diagram (Pin P86)
551
C.9
Port 9 Block Diagrams
Reset R Q D P90DDR C WP9D
Reset P90 R Q D P90DR C WP9
RP9
Internal data bus A/D converter External trigger input IRQ2 input IRQ enable register IRQ2 enable
WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9
Figure C.9 (a) Port 9 Block Diagram (Pin P9 0)
552
Reset R Q D P91DDR C WP9D
Reset P91 R Q D P91DR C WP9
RP9
Internal data bus IRQ1 input IRQ enable register IRQ1 enable PBI input bus (CS)
WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9
DPME Modes 1 and 2
Figure C.9 (b) Port 9 Block Diagram (Pin P91)
553
Reset R Q D P92DDR C WP9D
Reset P92 R Q D P92DR C WP9
RP9
Internal data bus IRQ0 input IRQ enable register IRQ0 enable
WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9
Figure C.9 (c) Port 9 Block Diagram (Pin P92)
554
DPME Mode 3
Modes 1 and 2
Reset R Q D P9nDDR C WP9D
Mode 3 P9n Modes 1 and 2
Reset R Q D P9nDR C WP9 RD output WR output
RP9
Internal data bus PBI
Hardware standby
WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 n = 3, 4
PBI input bus
CE input OE input
Figure C.9 (d) Port 9 Block Diagram (Pins P93, P94)
555
DPME Mode 3
Hardware standby Modes 1 and 2 Reset R Q D P95DDR C WP9D Reset R Q D P95DR C WP9 Internal data bus
PBI RDY output
P95
* Modes 1 and 2
AS output
RP9
WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Note: * NMOS open drain when DPME = 1 in mode 3.
Figure C.9 (e) Port 9 Block Diagram (Pin P95)
556
Hardware standby
Modes 1 and 2
Reset
SR Q D P96DDR C WP9D
*
P96
Internal data bus o
RP9
WP9D: Write to P9DDR Write to port 9 WP9: Read port 9 RP9: Note: * Set priority
Figure C.9 (f) Port 9 Block Diagram (Pin P96)
557
DPME Mode 3
Reset R Q D P97DDR C WP9D Reset R Q D P97DR C WP9
P97
RP9
WAIT input PBI WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 PBI input bus WE input
Figure C.9 (g) Port 9 Block Diagram (Pin P9 7)
558
Internal data bus
Modes 1 and 2
Appendix D Pin States
D.1 Port States in Each Mode
Port States
Mode 1 2 Reset L T Hardware Software Standby Mode Standby Mode T L (DDR = 1) L/keep (DDR = 0) keep 3 P27 to P2 0 A15 to A 8 TP 15 to TP8 3 P37 to P3 0 D7 to D0 1 2 keep T T keep*
2
Table D.1
Pin Name P17 to P1 0 A7 to A 0 TP 7 to TP0
Program Sleep Mode Execution Mode keep* 1 A7 to A 0 Address output or input port I/O port keep*
1
keep L T T L (DDR = 1) L/keep (DDR = 0) keep keep T T T T
1 2
A15 to A 8 Address output or input port I/O port D7 to D0
DDB7 to DDB 0 3 P47 to P4 0 1 2 3 P52 to P5 0 1 2 3 P67 to P6 0 1 2 3 P77 to P7 0 1 2 3 P86 to P8 0 1 2 3 T T T T T T T T
keep keep
I/O port I/O port
keep* 2
keep
I/O port
keep* 2
keep
I/O port
T
T
Input port
keep* 2
keep
I/O port
559
Table D.1
Pin Name P97/WAIT
Port States (cont)
Mode 1 2 3 keep Clock T output T H keep I/O port Reset T Hardware Software Standby Mode Standby Mode T T Program Sleep Mode Execution Mode T WAIT or I/O port
P96/o
1 2 3
Clock output Clock output
(DDR = 1) H (DDR = 0) T
Clock output Clock output (DDR = 1) or (DDR = 1) or T (DDR = 0) input port (DDR = 0) H AS, WR, RD
P95 to P9 3 AS, WR, RD
1 2 3
H
T
H
T T T
keep keep
keep keep
I/O port I/O port
P92 to P9 0
1 2 3
Legend H: High L: Low T: High-impedance state keep: Input pins are in the high-impedance state (with input pull-up on if PCR = 1) ; output pins maintain their previous state. Notes: 1. Address output pins hold the last address accessed. 2. On-chip supporting modules are initialized, so these pins revert to I/O ports controlled by their DDR and DR bits.
560
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode
Timing of Transition to Hardware Standby Mode (1) To retain RAM contents when the RAME bit in SYSCR is cleared to 0, drive the RES signal low 10 system clock cycles before the STBY signal goes low, as shown below. RES must remain low until STBY goes low (minimum delay from STBY low to RES high: 0 ns).
STBY t1 10 tcyc RES t2 0 ns
(2) When the RAME bit in SYSCR is set to 1 or when it is not necessary to retain RAM contents, RES does not have to be driven low as in (1). Timing of Recovery From Hardware Standby Mode: Drive the RES signal low approximately 100 ns before STBY goes high.
STBY t 100 ns RES tOSC
561
Appendix F Product Code Lineup
Table F.1 H8/3318 Product Code Lineup
Product Type H8/3318 ZTAT version Product Code HD6473318CG16 HD6473318CP16 HD6473318F16 HD6473318TF16 Mask ROM version HD6433318CP HD6433318F HD6433318TF Mark Code HD6473318CG16 HD6473318CP16 HD6473318F16 HD6473318TF16 HD6433318(***)CP HD6433318(***)F HD6433318(***)TF Package (Hitachi Package Code) 84-pin windowed LCC (CG-84) 84-pin PLCC (CP-84) 80-pin QFP (FP-80A) 80-pin TQFP (TFP-80C) 84-pin PLCC (CP-84) 80-pin QFP (FP-80A) 80-pin TQFP (TFP-80C)
Note: (***) in mask ROM version is the ROM code.
562
Appendix G Package Dimensions
Figure G.1 shows the dimensions of the FP-80A package. Figure G.2 shows the dimensions of the TFP-80C package. Figure G.3 shows the dimensions of the CP-84 package. Figure G.4 shows the dimensions of the CE-84 package
17.2 0.3
14
Unit: mm
41 40
60 61
17.2 0.3
80 1
*0.32 0.08 0.30 0.06
21 20
0.65
0.12 M 0.83
3.05 Max
*0.17 0.05 0.15 0.04
2.70
1.6
0.10 +0.15 -0.10
0 - 8
0.8 0.3
Hitachi Code JEDEC EIAJ Weight (reference value) FP-80A -- Conforms 1.2 g
0.10
*Dimension including the plating thickness Base material dimension
Figure G.1 Package Dimensions (FP-80A)
563
14.0 0.2 12 60 61 41 40
Unit: mm
14.0 0.2
80 1 *0.22 0.05 0.20 0.04 20 0.10 M 1.25
21
0.5
*0.17 0.05 0.15 0.04
1.20 Max
1.00
1.0 0 - 8 0.5 0.1
Hitachi Code JEDEC EIAJ Weight (reference value) TFP-80C -- Conforms 0.4 g
0.10
*Dimension including the plating thickness Base material dimension
Figure G.2 Package Dimensions (TFP-80C)
564
0.10 0.10
Unit: mm
30.23 +0.12 -0.13 29.28 74 75 54 53
30.23 +0.12 -0.13
84 1
11 12 0.75 1.94 32
33
4.40 0.20
2.55 0.15
0.20 M
1.27 *0.42 0.10 0.38 0.08 28.20 0.50
28.20 0.50 0.10
*Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Weight (reference value)
CP-84 Conforms Conforms 6.4 g
Figure G.3 Package Dimensions (CP-84)
0.90
565
29.21 0.38
Unit: mm
8.89
12 11
32 33
1 84 75 74 2.16 1.27 54
53 1.27
Hitachi Code JEDEC EIAJ Weight (reference value) CG-84 -- -- 8.96 g
Figure G.4 Package Dimensions (CG-84)
566
0.635
4.03 Max
H8/3318 Hardware Manual
Publication Date: 1st Edition, April 1996 2nd Edition, September 1999 Published by: Electronic Devices Sales & Marketing Group Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group UL Media Co., Ltd. Copyright (c) Hitachi, Ltd., 1996. All rights reserved. Printed in Japan.

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